DS2151 Dallas Semiconducotr, DS2151 Datasheet - Page 29

• Manufacturer Part Number: DS2151
• Description: T1 Single-Chip Transceiver
• Manufacturer: Dallas Semiconducotr

TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTERS (Address=39 to
3B Hex)
Each of the bit positions in the Transmit Transparency Registers (TTR1/TTR2/TTR3) represents a DS0
channel in the outgoing frame. When these bits are set to a 1, the corresponding channel is transparent
(or clear). If a DS0 is programmed to be clear, no Robbed-Bit signaling will be inserted nor will the
channel have Bit 7 stuffing performed. However, in the D4 framing mode, Bit 2 will be overwritten by a
0 when a Yellow Alarm is transmitted. Also the user has the option to prevent the TTR registers from
determining which channels are to have Bit 7 stuffing performed. If the TCR2.0 and TCR1.3 bits are set
to 1, then all 24 T1 channels will have Bit 7 stuffing performed on them regardless of how the TTR
registers are programmed. In this manner, the TTR registers are only affecting which channels are to
have Robbed-Bit signaling inserted into them. Please see Figure 13-9 for more details.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=3C to 3E Hex)
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=3F Hex)
Each of the bit positions in the Transmit Idle Registers (TIR1/TIR2/TIR3) represents a DS0 channel in
the outgoing frame. When these bits are set to a 1, the corresponding channel will transmit the Idle Code
contained in the Transmit Idle Definition Register (TIDR). Robbed-Bit signaling and Bit 7 stuffing will
occur over the programmed Idle Code unless the DS0 channel is made transparent by the Transmit
Transparency Registers.
(MSB)
(MSB)
CH16
CH24
CH16
CH24
CH8
(MSB)
TIDR7
CH8
CH15
CH23
CH7
CH15
CH23
CH7
TIDR6
SYMBOL POSITION NAME AND DESCRIPTION
SYMBOL POSITION NAME AND DESCRIPTION
SYMBOL POSITION NAME AND DESCRIPTION
TIDR7
TIDR0
CH24
CH24
CH14
CH22
CH1
CH1
CH6
CH14
CH22
CH6
TIDR5
TIDR.7
TIDR.0
TTR3.7
TTR1.0
TIR3.7
TIR1.0
CH13
CH21
CH5
CH13
CH21
CH5
TIDR4
MSB of the Idle Code
LSB of the Idle Code
Transmit Idle Registers.
0=do not insert the Idle Code into this DS0 channel
1=insert the Idle Code into this channel
Transmit Transparency Registers.
0=this DS0 channel is not transparent
1=this DS0 channel is transparent
CH12
CH20
CH4
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CH12
CH20
CH4
TIDR3
CH11
CH19
CH3
CH11
CH19
CH3
CH10
CH18
TIDR2
CH2
CH10
CH18
CH2
(LSB)
CH17
CH1
CH9
TIDR1
(LSB)
CH17
CH1
CH9
TIR1 (3C)
TIR2 (3D)
TIR3 (3E)
TTR2 (3A)
TTR3 (3B)
TTR1 (39)
TIDR0
(LSB)
DS2151Q