74HCT401 Philips, 74HCT401 Datasheet - Page 2

• Manufacturer Part Number: 74HCT401
• Description: 8-bit synchronous BCD down counter
• Manufacturer: Philips

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT40102 are high-speed Si-gate CMOS
devices and are pin compatible with the “40102” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT40102 consist each of an 8-bit
synchronous down counter with a single output which is
active when the internal count is zero. The “40102” is
configured as two cascaded 4-bit BCD counters and has
control inputs for enabling or disabling the clock (CP), for
clearing the counter to its maximum count, and for
presetting the counter either synchronously or
asynchronously. All control inputs and the terminal count
output (TC) are active-LOW logic.
In normal operation, the counter is decremented by one
count on each positive-going transition of the clock (CP).
Counting is inhibited when the terminal enable input (TE)
is HIGH. The terminal count output (TC) goes LOW when
the count reaches zero if TE is LOW, and remains LOW for
one full clock period.
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
December 1990
SYMBOL
t
f
C
C
PHL
max
Cascadable
Synchronous or asynchronous preset
Output capability: standard
I
8-bit synchronous BCD down counter
I
PD
CC
f
f
C
V
i
o
/ t
CC
PD
= input frequency in MHz
L
category: MSI
= output frequency in MHz
(C
PLH
= output load capacitance in pF
P
= supply voltage in V
is used to determine the dynamic power dissipation (P
L
D
= C
V
amb
CC
PD
PARAMETER
propagation delay CP to TC
maximum clock frequency
input capacitance
power dissipation capacitance per package
2
= 25 C; t
V
f
CC
o
) = sum of outputs
2
f
r
i
= t
f
= 6 ns
(C
L
V
CC
2
f
o
) where:
2
When the synchronous preset enable input (PE) is LOW,
data at the jam input (P
on the next positive-going clock transition regardless of the
state of TE. When the asynchronous preset enable input
(PL) is LOW, data at the jam input (P
asynchronously forced into the counter regardless of the
state of PE, TE, or CP. The jam inputs (P
two 4-bit BCD words.
When the master reset input (MR) is LOW, the counter is
asynchronously cleared to its maximum count (decimal
99) regardless of the state of any other input. The
precedence relationship between control inputs is
indicated in the function table.
If all control inputs except TE are HIGH at the time of zero
count, the counters will jump to the maximum count, giving
a counting sequence of 100 clock pulses long.
The “40102” may be cascaded using the TE input and the
TC output, in either a synchronous or ripple mode.
APPLICATIONS
D
Divide-by-n counters
Programmable timers
Interrupt timers
Cycle/program counters
CONDITIONS
C
notes 1 and 2
in W):
L
= 15 pF; V
CC
= 5 V
0
to P
7
74HC/HCT40102
) is clocked into the counter
30
30
3.5
20
HC
TYPICAL
Product specification
0
to P
31
30
3.5
25
0
HCT
to P
7
) is
7
) represent
UNIT
ns
MHz
pF
pF