PI90LV386 Pericom Semiconductor Corporation, PI90LV386 Datasheet

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PI90LV386

Manufacturer Part Number
PI90LV386
Description
High-Speed Differential Line Receivers
Manufacturer
Pericom Semiconductor Corporation
Datasheet

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Part Number
Manufacturer
Quantity
Price
Part Number:
PI90LV386A
Manufacturer:
PERICOM
Quantity:
3
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 1 2 3 4 5 6 7 8 9 0 1 2
Pin Configuration
Features
• Sixteen line receivers meet or exceed the requirements of the
• Designed for signaling rates up to 660 Mbps
• 0V to 3V common-mode input voltage range
• Operates from a single 3.3V supply
• Typical propagation delay time: 2.6ns
• Output skew 100ps (typical)
• Part-to-part skew is less than 1ns
• Integrated 110-Ohm termination on PI90LVT386
• Low Voltage TTL (LVTTL) levels are 5V tolerant
• Open-circuit fail safe
• Flow-through pin out
• Packaging (Pb-free & Green available):
ANSI TIA/EIA-644-1995 Standard
- 64-Pin Thin Shrink Small Output TSSOP (A)
1R IN1+
1R IN1–
1R IN2+
1R IN2–
1R IN3+
1R IN3–
1R IN4+
1R IN4–
2R IN1+
2R IN1–
2R IN2–
2R IN2–
2R IN3+
2R IN3–
2R IN4+
2R IN4–
3R IN1+
3R IN1–
3R IN2+
3R IN2–
3R IN3+
3R IN3–
3R IN4+
3R IN4–
4R IN1+
4R IN1–
4R IN2+
4R IN2–
4R IN3+
4R IN3–
4R IN4+
4R IN4–
16 Receivers
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64-Pin
A
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
GND
V CC
V CC
GND
EN1
1R OUT1
1R OUT2
1R OUT3
1R OUT4
EN2
2R OUT1
2R OUT2
2R OUT3
2R OUT4
GND
V CC
V CC
GND
3R OUT1
3R OUT2
3R OUT3
3R OUT4
EN3
4R OUT1
4R OUT2
4R OUT3
4R OUT4
EN4
GND
V CC
V CC
GND
1
Description
The PI90LVx386 family consists of sixteen differential line receivers
with 3-state outputs that implement Low-Voltage Differential
Signaling (LVDS). Any of the differential receivers will provide a
valid logical output state with a ±100mV differential input voltage
within the input common-mode voltage range that allows 0 to 3V of
ground potential difference between two LVDS nodes. The indepen-
dent EN pins can be used to place the outputs in either a normal logic
state (high or low logic levels) or a high-impedance state. In high-
impedance state, outputs neither load nor drive the bus lines.
The intended application of these devices, and their signaling
techniques, is for point-to-point baseband data transmission over
controlled impedance media of approximately 100-ohms with a
100-Ohm termination resistor. The PI90LVT386 integrates the termi-
nating resistors while the PI90LV386 requires external resistors.
The transmission media may be printed circuit board traces,
backplanes, or cables. The PI90LV386’s 16 receivers integrated into
the same substrate allow precise timing alignment.
These parts are characterized for operation from –40°C to 85°C.
Block Diagram
High-Speed Differential Line Receivers
PI90LV386/PI90LVT386
PS8574B
10/04/04

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PI90LV386 Summary of contents

Page 1

... PI90LV386 requires external resistors. The transmission media may be printed circuit board traces, backplanes, or cables. The PI90LV386’s 16 receivers integrated into the same substrate allow precise timing alignment. These parts are characterized for operation from –40°C to 85°C. ...

Page 2

... – PI90LV386/PI90LVT386 High-Speed Differential Line Receivers – – PS8574B ° ...

Page 3

... – PI90LV386/PI90LVT386 High-Speed Differential Line Receivers (unless otherwise noted – – ...

Page 4

... PLH PHL 4 PI90LV386/PI90LVT386 High-Speed Differential Line Receivers (unless otherwise noted ...

Page 5

... – – PI90LV386/PI90LVT386 High-Speed Differential Line Receivers R IN IN– ...

Page 6

... Mpps, Pulse width = 10 ±0.2ns IRIN+ 10pF V IRIN– t PHL 2.4V 0. Figure 2. Timing Test Circuit and Waveforms includes instrumentation and fixture capacitance within 0.06m of the D.U. PI90LV386/PI90LVT386 High-Speed Differential Line Receivers 1.4V 1V 0.4V 0V –0.4V t PLH 0V 1. ...

Page 7

... R IN– 1. 10pF EN includes instrumentation and fixture capacitance within 0.06m L t PZL t PLZ V OL +0.5V t PZH t PHZ V OL –0.5V Figure 3. Enable/Disable Test Circuit and Waveforms 7 PI90LV386/PI90LVT386 High-Speed Differential Line Receivers 500 Ohms + TEST – 1ns, Pulse Repetition 1.4V 0.8V 2 ...

Page 8

... Max. .002 .006 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Package Code A 64-pin TSSOP A Pb-free & Green, 64-pin TSSOP A 64-pin TSSOP A Pb-free & Green, 64-pin TSSOP 8 PI90LV386/PI90LVT386 High-Speed Differential Line Receivers .236 6.0 .244 6.2 0.45 .018 0.75 .030 SEATING PLANE .319 BSC 8.1 .004 0.10 0.05 0.15 Package Type .004 ...

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