SY10E142 Micrel Semiconductor, SY10E142 Datasheet

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SY10E142

Manufacturer Part Number
SY10E142
Description
9-BIT SHIFT REGISTER
Manufacturer
Micrel Semiconductor
Datasheet

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FEATURES
BLOCK DIAGRAM
700MHz min. shift frequency
Extended 100E V
9 bits wide for byte-parity applications
Asynchronous Master Reset
Dual clocks
Fully compatible with industry standard 10KH,
100K ECL levels
Internal 75K input pulldown resistors
Fully compatible with Motorola MC10E/100E142
Available in 28-pin PLCC package
CLK1
CLK2
S-IN
SEL
D
D
D
D
D
D
D
D
MR
D
1
2
3
4
5
6
7
8
0
EE
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
range of –4.2V to –5.5V
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
D Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
0
1
2
3
4
5
6
7
8
9-BIT SHIFT
REGISTER
1
designed for use in new, high-performance ECL systems.
The E142 can accept serial or parallel data to be shifted out
in one direction as both serial and parallel outputs. The
nine inputs, D
accepts serial input data.
mode of operation, either SHIFT or LOAD. The shift direction
is from bit 0 to bit 8. The input data has to meet the set-up
time before being clocked into the nine input registers on
the rising edge of CLK
on the rising edge of either CLK
Reset) control signal asynchronously resets all nine
registers to a logic LOW when a logic HIGH is applied to
MR.
scan registers, parallel-to-serial conversions and is also
suitable for byte-wide parity.
DESCRIPTION
PIN CONFIGURATION
PIN NAMES
The SY10/100E142 are high-speed 9-bit shift registers
The SEL (Select) control pin serves to determine the
The E142 is designed for applications such as diagnostic
D
S-IN
SEL
CLK
MR
Q
V
CLK
CLK
CCO
0
S-IN
0
V
-D
MR
Pin
-Q
EE
D
D
1
2
8
1
0
1
8
, CLK
0
-D
26
27
28
2
3
4
1
2
8
, accept parallel input data, while S-IN
25 24 23 22 21 20 19
5
1
or CLK
6
TOP VIEW
7
PLCC
J28-1
8
2
1
. Shifting is also performed
Parallel Data Inputs
Serial Data Input
Mode Select Input
Clock Inputs
Master Reset
Data Outputs
V
9
or CLK
CC
10 11
Function
to Output
2
Rev.: C
Issue Date: February, 1998
18
17
16
15
14
13
12
. The MR (Master
SY100E142
SY10E142
Q
Q
V
Q
V
Q
Q
CC
CCO
6
7
5
4
3
Amendment: /1

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SY10E142 Summary of contents

Page 1

... Q 6 PIN NAMES Q 7 Pin S- SEL CLK , CLK CCO 1 SY10E142 SY100E142 , accept parallel input data, while S- CLK . Shifting is also performed CLK . The MR (Master ...

Page 2

... SY10E142 SY100E142 Condition — — Condition — — — — — — 1 — ...

Page 3

... Micrel 28 LEAD PLCC (J28-1) 3 SY10E142 SY100E142 Rev. 03 ...

Page 4

... This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc (408) 914-7878 http://www.micrel.com FAX WEB © 2000 Micrel Incorporated 4 SY10E142 SY100E142 ...

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