AD7937 Analog Devices, AD7937 Datasheet - Page 5

• Manufacturer Part Number: AD7937
• Description: LC2MOS 8+4 Loading Dual 12-Bit DAC
• Manufacturer: Analog Devices

UNIPOLAR BINARY OPERATION
(2-QUADRANT MULTIPLICATION)
Figure 4 shows the circuit diagram for unipolar binary operation.
With an ac input, the circuit performs 2-quadrant multiplication.
The code table for Figure 4 is given in Table II.
Operational amplifiers A1 and A2 can be in a single package
(AD644, AD712) or separate packages (AD544, AD711,
AD OP27). Capacitors C1 and C2 provide phase compensation
to help prevent overshoot and ringing when high-speed op amps
are used.
For zero offset adjustment, the appropriate DAC register is loaded
with all 0s and amplifier offset adjusted so that V
is 0 V. Full-scale trimming is accomplished by loading the DAC
register with all 1s and adjusting R1 (R3) so that V
= –V
and potentiometers should have a low Temperature Coefficient.
In many applications, because of the excellent Gain T.C. and Gain
Error specifications of the AD7937, Gain Error trimming is not
necessary. In fixed reference applications, full scale can also be
adjusted by omitting R1, R2, R3, R4 and trimming the reference
voltage magnitude.
IN
INPUT
DATA
Binary Number in
DAC Register
MSB
1111 1111 1111
1000 0000 0000
0000 0000 0001
0000 0000 0000
(4095/4096). For high temperature operation, resistors
DB0
DB7
Table II. Unipolar Binary Code Table for
Circuit of Figure 4
DGND
V
DD
AD7937
V
V
DAC B
LSB
DAC A
INA
INB
R1
100
R3
100
R
R
I
AGNDB
I
AGNDA
OUTA
OUTB
FBA
FBB
CONTROL CIRCUITRY
OMITTED FOR CLARITY
47
47
Analog Output,
V
0 V
−V
−V
−V
R2
R4
OUTA
IN
IN
IN
C2
33pF
C1
33pF









or V
4095
4096
2048
4096
4096
1
A2
OUTB
A1




 = −




AD712
AD712
1/2
1/2
OUTA
OUTA
1
2
V
or V
V
V
OUTB
OUTA
IN
(V
OUTB
OUTB
)
BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)
The recommended circuit diagram for bipolar operation is shown
in Figure 5. Offset binary coding is used.
With the appropriate DAC register loaded to 1000 0000 0000,
adjust R1 (R3) so that V
R2 (R3, R4) may be omitted and the ratios of R6, R7 (R9, R10)
varied for V
accomplished by adjusting the amplitude of V
value of R5 (R8).
If R1, R2 (R3, R4) are not used, then resistors R5, R6, R7 (R8,
R9, R10) should be ratio matched to 0.01% to ensure gain error
performance to the data sheet specification. When operating over a
wide temperature range, it is important that the resistors be of
the same type so that their temperature coefficients match.
The code table for Figure 5 is given in Table III.
INPUT
DATA
DB7
DB0
DGND
Binary Number in
DAC Register
MSB
1111 1111 1111
1000 0000 0001
1000 0000 0000
0111 1111 1111
0000 0000 0000
Table III. Bipolar Code Table for Offset Binary
Circuit of Figure 5
V
DD
AD7937
OUTA
V
V
DAC A
DAC B
INB
INA
R3
100
R1
100
(V
LSB
OUTB
R
R
I
AGNDB
I
AGNDA
CONTROL CIRCUITRY
OMITTED FOR CLARITY
OUTB
OUTA
OUTA
FBB
FBA
) = 0 V. Full-scale trimming can be
47
47
R4
R2
(V
20k
20k
R10
R6
Analog Output,
V
0 V
OUTB
+V
+V
−V
−V
C1
33pF
C2
33pF
OUTA
IN
IN
IN
IN
) = 0 V. Alternatively, R1,












A3
or V
A1
AD712
2048
2048
2048
2047
2048
2048
AD712
10k
10k
1/2
1/2
1
1
R9
R7
IN
OUTB










 = −V

or by varying the
AD7937
20k
20k
A2
A4
R5
R8
AD712
AD712
IN
1/2
1/2
V
V
OUTA
OUTB