AD7874 Analog Devices, AD7874 Datasheet - Page 10

• Manufacturer Part Number: AD7874
• Description: LC2MOS 4-Channel/ 12-Bit Simultaneous Sampling Data Acquisition System
• Manufacturer: Analog Devices

AD7874
MICROPROCESSOR INTERFACING
The AD7874 high speed bus timing allows direct interfacing to
DSP processors as well as modern 16-bit microprocessors.
Suitable microprocessor interfaces are shown in Figures 12
through 16.
AD7874–ADSP-2100 Interface
Figure 12 shows an interface between the AD7874 and the
ADSP-2100. Conversion is initiated using a timer which allows
very accurate control of the sampling instant on all four chan-
nels. The AD7874 INT line provides an interrupt to the ADSP-
2100 when conversion is completed on all four channels. The
four conversion results can then be read from the AD7874 using
four successive reads to the same memory address. The follow-
ing instruction reads one of the four results (this instruction is
repeated four times to read all four results in sequence):
where MR0 is the ADSP-2100 MR0 register and
ADC is the AD7874 address.
AD7874–ADSP-2101/ADSP-2102 Interface
The interface outlined in Figure 12 also forms the basis for an
interface between the AD7874 and the ADSP-2101/ADSP-2102.
The READ line of the ADSP-2101/ADSP-2102 is labeled RD.
In this interface, the RD pulse width of the processor can be
programmed using the Data Memory Wait State Control Regis-
ter. The instruction used to read one of the four results is as
outlined for the ADSP-2100.
AD7874–TMS32010 Interface
An interface between the AD7874 and the TMS32010 is shown
in Figure 13. Once again the conversion is initiated using an ex-
ternal timer and the TMS32010 is interrupted when all four
conversions have been completed. The following instruction is
used to read the conversion results from the AD7874:
where D is Data Memory address and
ADC is the AD7874 address.
(ADSP-2101/
ADSP-2102)
ADSP-2100
Figure 12. AD7874–ADSP-2100 Interface
DMRD (RD)
DMD15
DMA13
DMA0
DMD0
IRQn
DMS
MR0 = DM(ADC)
* ADDITIONAL PINS OMITTED FOR CLARITY
IN D,ADC
ADDRESS BUS
DATA BUS
EN
DECODE
ADDR
INT
CS
RD
DB11
DB0
AD7874*
CONVST
TIMER
–10–
AD7874–TMS320C25 Interface
Figure 14 shows an interface between the AD7874 and the
TMS320C25. As with the two previous interfaces, conversion is
initiated with a timer and the processor is interrupted when the
conversion sequence is completed. The TMS320C25 does not
have a separate RD output to drive the AD7874 RD input di-
rectly. This has to be generated from the processor STRB and
R/W outputs with the addition of some logic gates. The RD sig-
nal is OR-gated with the MSC signal to provide the one WAIT
state required in the read cycle for correct interface timing.
Conversion results are read from the AD7874 using the follow-
ing instruction:
where D is Data Memory address and
ADC is the AD7874 address.
TMS32010
TMS320C25
Figure 14. AD7874–TMS320C25 Interface
Figure 13. AD7874–TMS32010 Interface
MEN
DEN
READY
PA2
PA0
D15
INT
STRB
D0
INTn
MSC
A15
R/W
D15
A0
D0
IS
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS BUS
DATA BUS
EN
DECODE
IN D,ADC
ADDR
ADDRESS BUS
EN
DECODE
ADDR
DATA BUS
TIMER
TIMER
INT
CONVST
CS
RD
DB11
DB0
AD7874*
INT
DB11
DB0
CONVST
CS
RD
AD7874*
REV. C