AD7871 Analog Devices, AD7871 Datasheet - Page 3

• Manufacturer Part Number: AD7871
• Description: LC2MOS Complete 14-Bit/ Sampling ADCs
• Manufacturer: Analog Devices

TIMING CHARACTERISTICS
Parameter
NOTES
1
2
3
4
5
6
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
V
V
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V
V
REF OUT, C
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to V
Operating Temperature Range
Storage Temperature Range . . . . . . . . . . . . –65 C to +150 C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300 C
Power Dissipation (Any Package) to +75 C . . . . . . . . 450 mW
Derates above +75 C by . . . . . . . . . . . . . . . . . . . . . 6 mW/ C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7871/AD7872 features proprietary ESD protection circuitry, permanent dam-
age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. D
Timing Specifications in bold print are 100% production tested. All other times are sample tested at +25 C to ensure compliance. All input signals are specified with
Serial timing is measured with a 4.7 k
t
t
SCLK mark/space ratio (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
SDATA will drive higher capacitive loads, but this will add to t
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
time of the part and is independent of bus loading.
6
7
DD
SS
IN
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Commercial (J, K Versions) . . . . . . . . . . . . . . 0 C to +70 C
Industrial (A, B Versions) . . . . . . . . . . . . . –40 C to +85 C
Extended (T Version) . . . . . . . . . . . . . . . –55 C to +125 C
and t
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
3
4
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
to AGND . . . . . . . . . . . . . . . . V
5
6
3
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
17
are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
REF
to AGND . . . . . . . . . . . . . . . . . . 0 V to V
Limit at T
(J, K, A, B Versions) (T Version)
50
0
60
0
70
57
5
50
0
0
100
440
155
140
20
4
100
60
120
200
0
0
0
MIN
, T
pull-up resistor on SDATA and SSTRB and a 2 k pull-up resistor on SCLK. The capacitance on all three outputs is 35 pF.
MAX
SS
1, 2
–0.3 V to V
Limit at T
50
0
75
0
70
70
5
50
0
0
100
440
155
150
20
4
100
60
120
200
0
0
0
(V
DD
= +5 V
12
since it increases the external RC time constant (4.7 k //C
DD
DD
DD
DD
MIN
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
, T
5%, V
MAX
DD
SS
–3–
= –5 V
Units
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
5%, AGND = DGND = O V. See Figures 9, 10, 11 and 12.)
Figure 2. Load Circuit for Output Float Delay
Figure 1. Load Circuit for Access Time
Conditions/Comments
CONVST Pulse Width
CS to RD Setup Time (Mode 1)
RD Pulse Width
CS to RD Hold Time (Mode 1)
RD to INT Delay
Data Access Time after RD
Bus Relinquish Time after RD
HBEN to RD Setup Time
HBEN to RD Hold Time
SSTRB to SCLK Falling Edge Setup Time
SCLK Cycle Time
SCLK to Valid Data Delay. C
SCLK Rising Edge to SSTRB
Bus Relinquish Time after SCLK
CS to RD Setup Time (Mode 2)
CS to BUSY Propagation Delay
Data Setup Time Prior to BUSY
CS to RD Hold Time (Mode 2)
HBEN to CS Setup Time
HBEN to CS Hold Time
7
, quoted in the Timing Characteristics is the true bus relinquish
L
) and hence the time to reach 2.4 V.
AD7871/AD7872
WARNING!
L
= 35 pF
ESD SENSITIVE DEVICE