AD7575 Analog Devices, AD7575 Datasheet
AD7575
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AD7575 Summary of contents
Page 1
... The AD7575 requires only a single +5 V supply and a low cost, 1.23 V bandgap reference in order to convert an input signal range ...
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... Offset error is measured with respect to an ideal first code transition that occurs at 1/2 LSB. 3 Sample tested at + ensure compliance. 4 Accuracy may degrade at conversion times other than those specified. 5 Power supply current is measured when AD7575 is inactive i.e., when BUSY = logic HIGH. Specifications subject to change without notice +1.23 V, AGND = DGND = ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7575 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... CONNECT TERMINOLOGY LEAST SIGNIFICANT BIT (LSB) Relative An ADC with 8-bits resolution can resolve 1 part in 2 Accuracy Package 256) of full scale. For the AD7575 with +2.46 V full-scale one 2 (LSB) Options LSB is 9.61 mV. 1 max R-18 TOTAL UNADJUSTED ERROR 1 max N-18 This is a comprehensive specification that includes full-scale ...
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... Figure possible to avoid starting another conversion on the second READ (see below). Conversion is initiated by executing a memory READ instruc- tion to the AD7575 address, causing CS and LOW. Data is also obtained from the AD7575 during this instruction. This is old data and may be disregarded if not required. BUSY goes LOW, indicating that conversion is in progress, and re- turns HIGH when conversion is complete ...
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... If CS and RD go LOW within falling clock edge, the AD7575 may or may not see that falling edge as the first of the three falling clock edges to the sampling instant. In this case, the sampling instant could vary by one clock period impor- tant to know the exact sampling instant, CS and RD should not go LOW within falling clock edge ...
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... Thus C becomes charged to within 1/4 LSB IN in 6.9 time constants or about 7 ns. Since the AD7575 requires two input clock cycles (at a clock frequency of 4 MHz) before going into the compare mode, there is ample time for the input voltage to settle before the first comparator decision is made. ...
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... AD7575 INTERNAL/EXTERNAL CLOCK The AD7575 can be used with its own internal clock or with an externally applied clock. In either case, the clock signal appear- ing at the CLK pin is divided internally by two to provide an internal clock signal for the AD7575. A single conversion lasts for 20 input clock cycles (10 internal clock cycles). ...
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... Figure 15 shows the circuit connections to achieve this, while the nominal transfer characteristic for unipolar opera- tion is given in Figure 16. Since the offset and full-scale errors on the AD7575 are very small, in many cases it will not be nec- essary to adjust out these errors. If calibration is required, the procedure is as follows: ...
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... Therefore, the AD589 contributes no addi- tional errors over temperature to the system errors, and the combined total unadjusted error specification for the AD589 and AD7575 is as per the total unadjusted error specification in this data sheet. With nonratiometric applications, however, the analog input range stays the same if the reference varies and a full-scale error is introduced ...
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... C max TC the change in reference voltage from will be from 1. 1.22724 V, a change of – 2.76 mV. This results in a change in the full-scale range of the ADC of –5.52 mV, since the full-scale range on the AD7575 Because the LSB size for the AD7575 is 9.61 mV, the REF AD589 introduces an additional full-scale error of – ...
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... AD7575 18-Lead Plastic DIP (N-18) 0.91 (23.12) 0.89 (22.61 0.26 (6.61) 0.24 (6.10 PIN 1 0.175 (4.45) 0.18 (4.58) 0.12 (3.05) MAX 0.02 (0.508) 0.105 (2.67) 0.065 (1.66) 0.015 (0.381) 0.095 (2.42) 0.045 (1.15) SEATING PLANE 18-Lead Cerdip (Q-18 0.310 (7.874) 0.260 (6.604 PIN 1 0.950 (24.13) MAX 0.060 (1.524) 0.180 (4.572) 0.015 (0.381) 0.140 (3.556) 0.200 (5.080) 0.125 (3.175) ...