AD745AN Analog Devices, AD745AN Datasheet - Page 9

• Manufacturer Part Number: AD745AN
• Description: Ultralow Noise/ High Speed/ BiFET Op Amp
• Manufacturer: Analog Devices

REV. C
HOW CHIP PACKAGE TYPE AND POWER DISSIPATION
AFFECT INPUT BIAS CURRENT
As with all JFET input amplifiers, the input bias current of the
AD745 is a direct function of device junction temperature, I
approximately doubling every 10 C. Figure 30 shows the
relationship between bias current and junction temperature for
the AD745. This graph shows that lowering the junction
temperature will dramatically improve I
The dc thermal properties of an IC can be closely approximated
by using the simple model of Figure 31 where current represents
power dissipation, voltage represents temperature, and resistors
represent thermal resistance ( in C/watt).
From this model T
determined in a particular application by using Figure 30
together with the published data for
The user can modify
sink such as the Aavid #5801.
the AD745 in chip form. Figure 32 shows bias current vs.
supply voltage with
used to predict bias current after
bias current will double for every 10 C. The designer using the
AD745 in chip form (Figure 33) must also be concerned with
both
mount technology used.
Typically,
for normal packages, this small power dissipation level may be
ignored. But, with a large hybrid substrate,
proportionately more of the total
Figure 30. Input Bias Current vs. Junction Temperature
JC
and
10
10
10
10
10
10
10
–11
–10
–12
JC
–6
–7
–8
–9
–60 –40
’s will be in the 3 C to 5 C/watt range; therefore,
T
T
P
T
WHERE:
Figure 31. Device Thermal Model
P
CA
J
A
IN
J
JC
CA
IN
, since
= DEVICE DISSIPATION
= AMBIENT TEMPERATURE
= JUNCTION TEMPERATURE
= THERMAL RESISTANCE – JUNCTION TO CASE
= THERMAL RESISTANCE – CASE TO AMBIENT
J
= T
JC
JA
–20
JUNCTION TEMPERATURE – C
JA
as the third variable. This graph can be
A
by use of an appropriate clip-on heat
JC
+
JA
0
can be affected by the type of die
JA
20
P
IN
JA
V = 15V
T = +25 C
S
CA
A
. Therefore, I
40
is also a variable when using
JA
JA
+ -
.
has been computed. Again
JA
60
B
T
and power dissipation.
A
.
80 100 120
JC
B
will dominate
can be
140
B
–9–
Figure 32. Input Bias Current vs. Supply Voltage for
Various Values of
Figure 33. Breakdown of Various Package Thermal
Resistance
REDUCED POWER SUPPLY OPERATION FOR
LOWER I
Reduced power supply operation lowers I
lowering both the total power dissipation and, second, by
reducing the basic gate-to-junction leakage (Figure 32). Figure
34 shows a 40 dB gain piezoelectric transducer amplifier, which
operates without an ac coupling capacitor, over the –40 C to
+85 C temperature range. If the optional coupling capacitor,
C1, is used, this circuit will operate over the entire –55 C to
+125 C temperature range.
T
A
B
100
Figure 34. A Piezoelectric Transducer
300
200
C1*
0
5
TRANSDUCER
*OPTIONAL DC BLOCKING CAPACITOR
**OPTIONAL, SEE TEXT
CASE
C
T = +25 C
T
A
100
10
JA
8
**
SUPPLY VOLTAGE – Volts
CT**
10
10k
T
10
8
J
A
AD745
(DIE MOUNT
TO CASE)
+
(J TO
DIE MOUNT)
B
A
B
=
+5V
–5V
JA
B
JC
= 165 C/W
JA
in two ways: first, by
JA
= 115 C/W
= 0 C/W
AD745
15