AD7416-7418 Analog Devices, AD7416-7418 Datasheet - Page 10

• Manufacturer Part Number: AD7416-7418
• Description: 10-Bit Digital Temperature Sensor (AD7416) and Single/Four-Channel ADC (AD7417/AD7418)
• Manufacturer: Analog Devices

AD7416/AD7417/AD7418
The AD7416 contains a temperature-only channel, the AD7417
has four analog input channels and a temperature channel, while
the AD7418 has two channels, a temperature channel and an
analog input channel. The temperature channel address for all
parts is the same, CH0. The address for the analog input channel
on the AD7418 is CH4. Table VI outlines the channel selection
on the parts, while Table VII shows the fault queue settings.
D7
0
0
0
0
1
T
The T
whose 9 MSBs store the T
format equivalent to the 9 MSBs of the temperature value regis-
ter. Bits 6 to 0 are unused.
T
The T
9 MSBs store the T
equivalent to the 9 MSBs of the temperature value register. Bits
6 to 0 are unused.
D15
MSB B7
ADC VALUE REGISTER (ADDRESS 04H)
The ADC value register is a 16-bit, read only register whose
10 MSBs store the value produced by the ADC in binary for-
mat. Bits 5 to 0 are unused. Table IX shows the ADC value
register with 10 MSBs containing the ADC conversion request.
D15
MSB B8
ADC Transfer Function
The designed code transitions occur at successive integer LSB
values (i.e., 1 LSB, 2 LSB, etc.). The LSB size is = REF/1024.
The ideal transfer function characteristic for the AD7417 and
AD7418 ADC is shown in Figure 6.
HYST
OTI
SETPOINT REGISTER (ADDRESS 03H)
SETPOINT REGISTER (ADDRESS 02H)
HYST
OTI
D14
D14
D6
0
0
1
1
0
D4
0
0
1
1
Setpoint Register is a 16-bit, read/write register whose
Setpoint Register is a 16-bit, read/write register
D13
B7
D13
B6
Table VII. Fault Queue Settings
Table VIII. Setpoint Registers
Table VI. Channel Selection
D5
0
1
0
1
0
OTI
D12
B6
D3
0
1
0
1
D12
B5
setpoint in twos complement format
HYST
Table IX.
Channel Selection
Temperature Sensor (All Parts)
AIN1 (AD7417 Only)
AIN2 (AD7417 Only)
AIN3 (AD7417 Only)
AIN4 (AD7417) and AIN (AD7418)
D11
B5
D11
B4
setpoint in twos complement
D10
B4
Number of Faults
1 (Power Up Default)
2
4
6
D10
B3
B3
D9
D9
B2
D8
B2
D8
B1
D7
B1
D7
LSB
D6
LSB
–10–
CONFIG2 REGISTER (ADDRESS 05H)
A second configuration register is included in the AD7417/
AD7418 for the functionality of the CONVST pin. It is an 8 bit
register with bits D5 to D0 being left at 0. Bit D7 determines
whether the AD7417/AD7418 should be operated in its default
mode (D7 = 0), performing conversions every 355 s or in
CONVST pin mode (D7 = 1), where conversions will start only
when the CONVST pin is used. Bit 6 contains the Test 1 bit.
When this bit is 0 the I
disables the filters.
D7
Conversion Mode
SERIAL BUS INTERFACE
Control of the AD7416/AD7417/AD7418 is carried out via the
I
connected to this bus as a slave device, under the control of a
master device, e.g., the processor.
SERIAL BUS ADDRESS
As with all I
have a 7-bit serial address. The four MSBs of this address for
the AD7416 are set to 1001, the AD7417 are 0101, while the
three LSBs can be set by the user by connecting the A2 to A0
pins to either +V
up to eight AD7416/AD7417s can be connected to a single
serial bus, or the addresses can be set to avoid conflicts with
other devices on the bus. The four MSBs of this address for the
AD7418 are 0101, while the three LSBs are all set to zero.
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
2
C-compatible serial bus. The AD7416/AD7417/AD7418 is
condition, defined as a high-to-low transition on the serial
data line SDA while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition, and shift in the next eight bits, consisting
of a 7-bit address (MSB first) plus a R/W bit, which deter-
mines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl-
edge Bit. All other devices on the bus now remain idle while
The peripheral whose address corresponds to the transmitted
2
C-compatible devices, the AD7416/AD7417/AD7418
111...111
111...110
111...000
011...111
000...010
000...001
000...000
S
or GND. By giving them different addresses,
0V 1/2LSB
D6
Test 1 0
2
C filters are enabled (default). A 1
Figure 6.
Table X.
D5
ANALOG INPUT
1LSB = V
D4
0
+V
REF
–1LSB
D3
0
REF
/1024
D2
0
D1
0
REV. B
D0
0