AD5282 Analog Devices, AD5282 Datasheet - Page 8

• Manufacturer Part Number: AD5282
• Description: +15V/ I2C Compatible Digital Potentiometers
• Manufacturer: Analog Devices

AD5280/AD5282
A repeated Write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the Write cycle, each Data byte will
update the RDAC output. For example, after the RDAC has
acknowledged its Slave Address and Instruction Bytes, the
RDAC output will update after these two bytes. If another byte
is written to the RDAC while it is still addressed to a specific
slave device with the same instruction, this byte will update the
output of the selected slave device. If different instructions are
needed, the Write mode has to start with a new Slave Address,
Instruction, and Data Bytes again. Similarly, a repeated Read
function of the RDAC is also allowed.
MULTIPLE DEVICES ON ONE BUS
Figure 5 shows four AD5282 devices on the same serial bus.
Each has a different slave address sine the state of their AD0 and
AD1 pins are different. This allows each RDAC within each
device to be written to or read from independently. The master
device output bus line drivers are open-drain pull downs in a
fully I
Figure 5. Multiple AD5282 Devices on One Bus
LEVEL SHIFT FOR BI-DIRECTIONAL INTERFACE
While most old systems may be operated at one voltage, a new
component may be optimized at another. When two systems
operate the same signal at two different voltages, proper method
of level shifting is needed. For instance, one can use a 3.3V
E
shift scheme is needed in order to enable a bi-directional
communication so that the setting of the digital potentiometer
can be stored to and retrieved from the E
shows one of the techniques. M1 and M2 can be N-Ch FETs
2N7002 or low threshold FDV301N if V
Information contained in this Product Concept Data Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final
product in its present form. For latest information contact Walt Heinzer/Analog Devices, Santa Clara, CA. TEL [phone]; FAX [phone]; email; [e-mail]
MASTER
2
PROM to interface with a 5V digital potentiometer. A level
condition, Figure 2. In Read mode, the master will issue a
No Acknowledge for the 9
remains high). The master will then bring the SDA line low
before the 10
STOP condition, Figure 3.
2
C compatible interface.
AD1
AD0
SDA SCL
AD5282
th
Rp
clock pulse which goes high to establish a
VDD
Rp
AD1
AD0
SDA SCL
AD5282
PRELIMINARY TECHNICAL DATA
th
+5V
clock pulse (i.e., the SDA line
VDD
DD
AD1
AD0
falls below 2.5V.
SDA SCL
AD5282
2
PROM. Figure 6
VDD
AD1
AD0
SDA SCL
AD5282
SDA
SCL
8
SDA 1
SCL1
Figure 6. Level Shift for different potential operation.
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in figure 7. Applies to
digital input pins SDA, SCL, and SHDN.
V DD1 = 3.3V
Figure 8. ESD Protection of Resistor Terminals
Figure 7. ESD Protection of digital pins
E 2 PROM
3.3V
Rp
A,B,W
340
Rp
V
V SS
S
SS
G
M1
D
S
G
M2
LOGIC
Rp
D
REV PrE 12 MAR 02
Rp
AD5282
5V
V DD2 = 5V
SDA 2
SCL2