LTC3789 LINER [Linear Technology], LTC3789 Datasheet - Page 33

• Manufacturer Part Number: LTC3789
• Description: High Voltage High Current Controller for Battery Charging and Power Management
• Manufacturer: LINER [Linear Technology]

applicaTions inForMaTion
In Figure 22 the battery is approximated to be a signal
ground in series with the internal battery resistance R
Therefore, the simplified loop transmission is as follows:
where Gmo
the output current of the external DC/DC converter,
R
R
LOAD node to GND.
The Battery Charge Current Regulation Loop
This final regulation loop combines certain dynamic char-
acteristics that are found in all the other three loops. The
feedback signal for this charge current regulation loop is
the sense voltage across the charge current sense resis-
tor (R
compared to the voltage on the CL pin by the transcon-
ductance error amplifier (A5). In a familiar fashion, this
amplifier drives the output transconductance amplifier
(A10) to appropriately adjust the voltage on the ITH pin
driving the external DC/DC converter to regulate the input
current across the sense resistor (R
Due to the presence of the instant-on feature, description
of the charge current regulation loop has to be divided into
two separate operating regions. These regions of operation
depend on whether the voltage on the OFB pin is higher
or lower than the instant-on threshold (V
BFB
BAT
L
⎡
⎢
⎣
R
BV
R
) represents the effective output resistance from the
BFB2
= R
CS
BFB
(s) = g
). This voltage is amplified by a factor of 20 and
BFB1
⎤
⎥ •
⎦
p
(s) is the transfer function from V
⎡
⎢
⎣
m6
R
+ R
LB
⎡
⎢
⎢
⎢
⎢
⎣
⎛
⎜
⎝
BFB2
R
R
• C
LB
C
L
, and R
–
s + 1
g
m10
C
1
⎤
⎥ • Gmo
⎦
C
s
LB
⎞
⎟ C
⎠
= R
C
s + 1
p
CS
L
(s)
//(R
).
⎤
⎥
⎥
⎥
⎥
⎦
•
OUT(INST_ON)
DS(ON)
+ R
ITH
CS
BAT
).
to
+
.
The Battery Charge Current Regulation Loop when
V
In this operating region, the external charging PFET’s gate
is driven low and clamped at V
loop is shown in Figure 23.
The simplified loop transmission is:
where Gmo
the output current of the external DC/DC converter, R
R
resistance value resulting from the parallel combination
of R
OFB
CS
Figure 23. Simplified Linear Model of the Charge Current
Regulation Loop with the External Charging PFET Driven On
BIAS

L
20R
⎡
⎢
⎢
⎣
(
CC
L
+ R
R
R
> V
O10
50µA/
5µA
and R
R
L
(s) = g
1V
CS
O5
DS(ON)
 R
OUT(INST_ON)
ITH
•
CL
R
⎡
⎢
⎢
⎣
f
g
f
1
R
p
.
m10
CL
)
(
C
(s) is the transfer function from V
m5
C
R1+ R2
g
(
A10
+ R
L
m5
= 0.1m
R2 • C
s + 1
C
⎡
⎢
⎢
⎢
⎢
⎣
A5
= 0.5m
C
⎛
⎜
⎝
BAT
R
R1
60k
C
⎤
⎥
⎥
⎦
CC
, and R
IBMON
)
–
• Gmo
C
g
m8
IBMON
IBMON
g
R2
20k
C
m10
= 0.33m
C
A8
1
IBMON
C
s + 1
L
s
p
+
–
//R
s + 1
(s)
BGATE(ON)
⎞
⎟ C
⎠
LTC4000
)
f
C
represents the effective
CSN
s + 1
CSP
BAT
⎤
⎥
⎥
⎦
•
R
4000 F23
⎤
⎥
⎥
⎥
⎥
⎦
f
LTC4000
. The detail of this
•
R
+ R
L
+
–
INPUT
L
R
R
R
•
CS
DS(ON)
BAT
Gmo
33
p
(s)
C
ITH
L
4000f
f
R
to
L
=