S3S12HZ256J3CAA FREESCALE [Freescale Semiconductor, Inc], S3S12HZ256J3CAA Datasheet - Page 314

• Manufacturer Part Number: S3S12HZ256J3CAA
• Description: HCS12 Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 11 Inter-Integrated Circuit (IICV2)
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of
tap2tap column in
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the
The equation used to generate the divider values from the IBFD bits is:
314
SCL
SDA
SCL Divider = MUL x {2 x (scl2tap + [(SCL_Tap -1) x tap2tap] + 2)}
SDA
SCL
START condition
Table
11-4. The SCL Tap is used to generated the SCL period and the SDA Tap is used
Table
11-4, all subsequent tap points are separated by 2
Figure 11-4. SCL Divider and SDA Hold
MC9S12HZ256 Data Sheet, Rev. 2.04
Table 11-5. Multiplier Factor
SCL Hold(start)
IBC7-6
00
01
10
11
SCL Divider
RESERVED
MUL
01
02
04
STOP condition
SDA Hold
IBC5-3
Table
Freescale Semiconductor
SCL Hold(stop)
as shown in the
11-5.