RM5231A-300-H PMC [PMC-Sierra, Inc], RM5231A-300-H Datasheet - Page 15

• Manufacturer Part Number: RM5231A-300-H
• Manufacturer: PMC [PMC-Sierra, Inc]

Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
Document ID: PMC-2002174, Issue 2
3.10 Floating-Point General Register File
Table 2 Floating-Point Instruction Cycles
The floating-point general register file (FGR) is made up of thirty-two 64-bit registers. With the
floating-point load and store double instructions ( LDC1 and SDC1 ), the floating-point unit can
take advantage of the 64-bit wide data cache and issue a floating-point co-processor load or store
doubleword instruction in every cycle.
The floating-point control register space contains two registers; one for determining configuration
and revision information for the coprocessor and one for control and status information. These are
primarily used for diagnostic software, exception handling, state saving and restoring, and control
of rounding modes. To support superscalar operation, the FGR has four read ports and two write
ports, and is fully bypassed to minimize operation latency in the pipeline. Three of the read ports
and one write port are used to support the combined multiply-add instruction while the fourth read
and second write port allows a concurrent floating-point load or store.
Operation
fadd
fsub
fmult
fmadd
fmsub
fdiv
fsqrt
frecip
frsqrt
fcvt.s.d
fcvt.s.w
fcvt.s.l
fcvt.d.s
fcvt.d.w
fcvt.d.l
fcvt.w.s
fcvt.w.d
fcvt.l.s
fcvt.l.d
fcmp
fmov
fmovc
fabs
fneg
Note
1.
Numbers are represented as single/double precision format.
Latency
4
4
4/5
4/5
4/5
21/36
21/36
21/36
38/68
4
6
6
4
4
4
4
4
4
4
1
1
1
1
1
RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet
Repeat Rate
1
1
1/2
1/2
1/2
19/34
19/34
19/34
36/66
1
3
3
1
1
1
1
1
1
1
1
1
1
1
1
Preliminary
15