LTC2351-12 LINER [Linear Technology], LTC2351-12 Datasheet - Page 4

• Manufacturer Part Number: LTC2351-12
• Description: 6 Channel, 12-Bit, 1.5Msps Simultaneous Sampling ADC with Shutdown
• Manufacturer: LINER [Linear Technology]

POWER REQUIRE E TS
LTC2351-12
range, otherwise specifications are at T
SYMBOL
V
I
PD
TI I G CHARACTERISTICS
range, otherwise specifications are at T
SYMBOL
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2: All voltage values are with respect to ground GND.
Note 3: When these pins are taken below GND or above V
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
Note 4: Offset and range specifications apply for a single-ended CH0
CH5
reference.
Note 5: Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band. Linearity is tested for CH0 only.
Note 6: Guaranteed by design, not subject to test.
Note 7: Recommended operating conditions.
Note 8: The analog input range is defined for the voltage difference
between CHx
4
DD
SAMPLE(MAX)
THROUGHPUT
SCK
CONV
1
2
3
4
5
6
7
8
9
10
11
DD
W
, V
+ I
+
input with CH0
CC
CC
U
+
PARAMETER
Supply Voltage
Supply Current
Power Dissipation
and CHx
PARAMETER
Maximum Sampling Frequency per Channel
(Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
Conversion Time
Minimum High or Low SCLK Pulse Width
CONV to SCK Setup Time
SCK Before CONV
Minimum High or Low CONV Pulse Width
SCK↑ to Sample Mode
CONV↑ to Hold Mode
96th SCK↑ to CONV↑ Interval (Affects Acquisition Period)
Minimum Delay from SCK to Valid Bits 0 Through 11
SCK↑ to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
–
Settling Time After Sleep-to-Wake Transition
– CH5
–
, x = 0–5.
–
grounded and using the internal 2.5V
W U
DD
without latchup.
A
A
= 25°C. V
= 25°C. With internal reference, V
The
CONDITIONS
Active Mode, f
Nap Mode
Sleep Mode
Active Mode with SCK, f
DD
DD
, they will be
●
The
= 3V.
denotes the specifications which apply over the full operating temperature
●
denotes the specifications which apply over the full operating temperature
+
SAMPLE
–
= 1.5Msps
CONDITIONS
(Note 16)
(Notes 6, 17)
(Note 6)
(Notes 6, 10)
(Note 6)
(Note 6)
(Note 6)
(Notes 6, 11)
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 14)
SAMPLE
Note 9: The absolute voltage at CHx
Note 10: If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11: Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12: The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13: The time period for acquiring the input signal is started by the
96th rising clock and it is ended by the rising edge of CONV.
Note 14: The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15: The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
Note 16: Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17: The conversion process takes 16 clocks for each channel that is
enabled, up to 96 clocks for all 6 channels.
DD
= 1.5Msps
= V
CC
= 3V.
●
●
●
●
●
MIN
P-P
250
1.2
40
96
45
2
3
0
4
4
2
MIN
input sine wave.
2.7
+
and CHx
TYP
2
16.5
–
TYP
3.0
5.5
1.5
4.0
must be within this range.
10000
10000
MAX
4
8
6
MAX
3.6
15
8
2
SCLK cycles
UNITS
UNITS
235112f
mW
kHz
mA
mA
ms
µA
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V