LTC2054HV LINER [Linear Technology], LTC2054HV Datasheet - Page 7

• Manufacturer Part Number: LTC2054HV
• Description: Low Power Zero-Drift Operational Amplifiers
• Manufacturer: LINER [Linear Technology]

TEST CIRCUITS
Clock Feedthrough, Input Bias Current
The LTC2054 uses auto-zeroing circuitry to achieve an
almost zero DC offset over temperature, common mode
voltage, and power supply voltage. The frequency of the
clock used for auto-zeroing is typically 1.0kHz. The term
clock feedthrough is broadly used to indicate visibility of
this clock frequency in the op amp output spectrum. There
are typically two types of clock feedthrough in auto zeroed
op amps like the LTC2054.
The first form of clock feedthrough is caused by the
settling of the internal sampling capacitor and is input
referred; that is, it is multiplied by the closed loop gain of
the op amp. This form of clock feedthrough is independent
of the magnitude of the input source resistance or the
magnitude of the gain setting resistors. The LTC2054 has
a residue clock feedthrough of less then 0.2 V
referred at 1.0kHz.
The second form of clock feedthrough is caused by the
small amount of charge injection occurring during the
sampling and holding of the op amp’s input offset voltage.
The current spikes are multiplied by the impedance seen
at the input terminals of the op amp, appearing at the
output multiplied by the closed loop gain of the op amp. To
APPLICATIONS
10
Electrical Characteristics
4
3
Test Circuit
–
+
LTC2054
100k
V
V
+
–
2
5
U
1
INFORMATION
R
U
L
OUTPUT
2054 TC01
W
RMS
U
10
input
4
3
+
–
FOR 1Hz NOISE BW INCREASE ALL THE CAPACITORS BY A FACTOR OF 10.
LTC2054
100k
reduce this form of clock feedthrough, use smaller valued
gain setting resistors and minimize the source resistance
at the input. If the resistance seen at the inputs is less than
10k, this form of clock feedthrough is less than the amount
of residue clock feedthrough from the first form described
above.
Placing a capacitor across the feedback resistor reduces
either form of clock feedthrough by limiting the bandwidth
of the closed loop gain.
Input bias current is defined as the DC current into the
input pins of the op amp. The same current spikes that
cause the second form of clock feedthrough described
above, when averaged, dominate the DC input bias current
of the op amp below 70 C.
At temperatures above 70 C, the leakage of the ESD
protection diodes on the inputs increases the input bias
currents of both inputs in the positive direction, while the
current caused by the charge injection stays relatively
constant. At elevated temperatures (above 85 C) the
leakage current begins to dominate and both the negative
and positive pin’s input bias currents are in the positive
direction (into the pins).
1
DC-10Hz Noise Test Circuit
0.1 F
158k
LTC2054/LTC2054HV
316k
0.01 F
475k
475k
+
–
LT1012
0.01 F
TO X-Y
RECORDER
2054 TC02
7
2054f