LTC1878 LINER [Linear Technology], LTC1878 Datasheet - Page 11

• Manufacturer Part Number: LTC1878
• Description: High Efficiency Monolithic Synchronous Step-Down Regulator
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
external and internal frequencies are the same but exhibit
a phase difference, the current sources turn on for an
amount of time corresponding to the phase difference.
Thus the voltage on the PLL LPF pin is adjusted until the
phase and frequency of the external and internal oscilla-
tors are identical. At this stable operating point the phase
comparator output is high impedance and the filter
capacitor C
The loop filter components C
current pulses from the phase detector and provide a
stable input to the voltage controlled oscillator. The filter
component’s C
acquires lock. Typically R
0.01 F. When not synchronized to an external clock, the
internal connection to the VCO is disconnected. This
disallows setting the internal oscillator frequency by a DC
voltage on the V
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses in LTC1878 circuits: V
losses. The V
efficiency loss at very low load currents whereas the I
loss dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence as illustrated in Figure 6.
1. The V
Efficiency = 100% – (L1 + L2 + L3 + ...)
the DC bias current as given in the electrical character-
istics and the internal main switch and synchronous
switch gate charge currents. The gate charge current
results from switching the gate capacitance of the
IN
quiescent current is due to two components:
LP
holds the voltage.
IN
LP
PLL LPF
quiescent current loss dominates the
and R
U
pin.
LP
U
LP
determine how fast the loop
= 10k and C
IN
LP
quiescent current and I
and R
W
LP
smooth out the
LP
is 2200pF to
U
2
2
R
R
2. I
Other losses including C
losses and inductor core losses generally account for less
than 2% total additional loss.
internal power MOSFET switches. Each time the gate is
switched from high to low to high again, a packet of
charge dQ moves from V
dQ/dt is the current out of V
the DC bias current. In continuous mode, I
f(Q
internal top and bottom switches. Both the DC bias and
gate charge losses are proportional to V
their effects will be more pronounced at higher supply
voltages.
internal switches, R
continuous mode the average output current flowing
through inductor L is “chopped” between the main
switch and the synchronous switch. Thus, the series
resistance looking into the SW pin is a function of both
top and bottom MOSFET R
(DC) as follows:
The R
be obtained from the Typical Performance Charateristics
curves. Thus, to obtain I
R
output current.
2
L
R losses are calculated from the resistances of the
R
T
and multiply the result by the square of the average
SW
+ Q
0.00001
0.0001
DS(ON)
0.001
0.01
= (R
B
0.1
) where Q
1
Figure 6. Power Lost vs Load Current
0.1
DS(ON)TOP
V
L = 10 H
Burst Mode OPERATION
for both the top and bottom MOSFETs can
IN
= 4.2V
V
V
V
OUT
OUT
OUT
1
T
LOAD CURRENT (mA)
= 1.5V
= 2.5V
= 3.3V
and Q
SW
)(DC) + (R
, and external inductor R
IN
2
10
R losses, simply add R
B
IN
IN
and C
are the gate charges of the
DS(ON)
that is typically larger than
to ground. The resulting
100
DS(ON)BOT
OUT
and the duty cycle
1878 F06
ESR dissipative
LTC1878
1000
)(1 – DC)
IN
GATECHG
and thus
11
SW
L
. In
to
=