LTC1871-7 LINER [Linear Technology], LTC1871-7 Datasheet

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LTC1871-7

Manufacturer Part Number
LTC1871-7
Description
High Input Voltage,Current Mode Boost, Flyback and SEPIC Controller
Manufacturer
LINER [Linear Technology]
Datasheet
FEATURES
APPLICATIONS
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TYPICAL APPLICATION
Optimized for High Input Voltage Applications
Wide Chip Supply Voltage Range: 6V to 36V
Internal 7V Low Dropout Voltage Regulator
Optimized for 6V-Rated MOSFETs
Current Mode Control Provides Excellent
Transient Response
High Maximum Duty Cycle (92% Typ)
±2% RUN Pin Threshold with 100mV Hysteresis
±1% Internal Voltage Reference
Micropower Shutdown: I
Programmable Operating Frequency
(50kHz to 1MHz) with One External Resistor
Synchronizable to an External Clock Up to 1.3 × f
User-Controlled Pulse Skip or Burst Mode
Output Overvoltage Protection
Can be Used in a No R
Small 10-Lead MSOP Package
Telecom Power Supplies
42V Automotive Systems
24V Industrial Controls
IP Phone Power Supplies
36V TO 72V
2.2nF
V
26.7k
110k
IN
SENSE
Figure 1. Small, Nonisolated 12V Flyback Telecom Housekeeping Supply
Q
3.4k
12.4k
= 10μA
™ Mode for V
604k
120k
RUN
I
FB
FREQ
MODE/SYNC
TH
LTC1871-7
®
Operation
DS
INTV
SENSE
2.2μF
100V
X7R
GATE
GND
V
< 36V
CC
IN
OSC
100k
D1
9.1V
DESCRIPTION
The LTC
SEPIC controller optimized for driving 6V-rated MOSFETs
in high voltage applications. The LTC1871-7 works equally
well in low or high power applications and requires few
components to provide a complete power supply solution.
The switching frequency can be set with an external resistor
over a 50kHz to 1MHz range, and can be synchronized to
an external clock using the MODE/SYNC pin. Burst Mode
operation at light loads, a low minimum operating supply
voltage of 6V and a low shutdown quiescent current of
10μA make the LTC1871-7 well suited for battery-operated
systems. For applications requiring constant frequency
operation, Burst Mode operation can be defeated using
the MODE/SYNC pin. The LTC1871-7 is available in the
10-lead MSOP package.
PARAMETER
INTV
INTV
INTV
L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation.
No R
property of their respective owners.
Q1
FMMT625
4.7μF
X5R
10Ω
SENSE
Flyback and SEPIC Controller
CC
CC
CC
is a trademark of Linear Technology Corporation. All other trademarks are the
UV
UV
®
1871-7 is a current mode, boost, fl yback and
0.1μF
X5R
+
3:1
M1
FDC2512
0.12Ω
T1
VP1-0076
10BQ060
Current Mode Boost,
4148
D2
D3
High Input Voltage,
LTC1871-7
7.0V
5.6V
4.6V
47μF
16V
X5R
18717 F01
V
12V
0.4A
OUT
LTC1871-7
LTC1871
5.2V
2.1V
1.9V
18717fc
1

Related parts for LTC1871-7

LTC1871-7 Summary of contents

Page 1

... LTC1871-7 well suited for battery-operated systems. For applications requiring constant frequency operation, Burst Mode operation can be defeated using OSC ® Operation the MODE/SYNC pin. The LTC1871-7 is available in the 10-lead MSOP package. < 36V DS PARAMETER INTV CC ...

Page 2

... LTC1871-7 ABSOLUTE MAXIMUM RATINGS (Note 1) V Voltage ............................................... – 0.3V to 36V IN INTV Voltage ............................................ –0. INTV Output Current .......................................... 50mA CC GATE Voltage ............................ –0. Voltages ....................................... –0.3V to 2.7V TH RUN Voltage ............................................... –0. MODE/SYNC Voltage .................................... –0. FREQ Voltage ............................................ –0.3V to 1.5V SENSE Pin Voltage .................................... –0.3V to 36V Operating Temperature Range (Note 2) LTC1871E-7 ......................................... – ...

Page 3

... OSC f = 300kHz (Note 6), I-Grade (Note 2) OSC SYNC SYNC I-Grade (Note 2) I-Grade (Note 8V, I-Grade (Note 2) IN LTC1871-7 = 0V, unless otherwise specifi ed. MODE/SYNC MIN TYP MAX UNITS 1.348 1.223 1.248 1.273 ● 1.198 1.298 50 100 150 mV ● ...

Page 4

... L Note 4: The dynamic input supply current is higher due to power MOSFET gate charging (Q Note 5: The LTC1871-7 is tested in a feedback loop that servos V reference voltage with the I (the no load to full load operating voltage range for the I 1.23V). Note synchronized application, the internal slope compensation gain is increased by 25%. Synchronizing to a signifi ...

Page 5

... FREQUENCY (kHz) RUN Thresholds vs Temperature 1.40 1.35 1.30 1.25 1.20 40 –50 – 100 TEMPERATURE (°C) LTC1871-7 Burst Mode 600 500 400 300 200 100 (V) IN 18717 G05 Gate Drive Rise and Fall Time ...

Page 6

... LTC1871-7 TYPICAL PERFORMANCE CHARACTERISTICS Frequency vs Temperature 325 320 315 310 305 300 295 290 285 280 275 –50 50 100 125 150 – TEMPERATURE (°C) 18717 G13 INTV Load Regulation 7.0 6.9 6 INTV LOAD (mA) CC 18717 G16 ...

Page 7

... OSC I OSC PWM LATCH S 50k R BURST CURRENT COMPARATOR COMPARATOR + 0.30V – V-TO-I I LOOP 1.230V SLOPE 1.230V TO START-UP BIAS V REF CONTROL V IN LTC1871-7 is less than 36V. Internal leading DS RUN + 1 C2 – 1.248V INTV CC GATE 7 LOGIC Q GND SENSE + 10 C1 – R LOOP GND 6 18717 BD ...

Page 8

... F02 the duration of an output overvoltage condition. > 36V SW The LTC1871-7 can be used either by sensing the voltage drop across the power MOSFET or by connecting the SENSE pin to a conventional shunt resistor in the source of the power MOSFET, as shown in Figure 2. Sensing the voltage across the power MOSFET maximizes converter effi ...

Page 9

... IC be programmed to be about 75% of the external clock frequency. Attempting to synchronize to too high an V OUT 50mV/DIV I L 5A/DIV 18717 F03 Figure 4. LTC1871-7 Low Output Current Operation with Burst Mode Operation Disabled (MODE/SYNC = INTV LTC1871-7 burst clamp is removed, allowing the I pin is driven below TH MODE/SYNC = INTV CC (PULSE SKIP MODE) 18717 F04 2μ ...

Page 10

... Figure 5. MODE/SYNC Clock Input and Switching Waveforms for Synchronized Operation 10 logic circuitry within the LTC1871-7, as shown in Figure 7. The INTV CC bypassed to ground immediately adjacent to the IC pins with a minimum of 4.7μF tantalum or ceramic capacitor. Good bypassing is necessary to supply the high transient currents required by the MOSFET gate driver. ...

Page 11

... OPERATION – 1.230V + R2 Figure 7. Bypassing the LDO Regulator and Gate Driver Supply can cause the LTC1871-7 to exceed its maximum junc- tion temperature rating. The junction temperature can be estimated using the following equations: I ≈ • Q Q(TOT • • Q ...

Page 12

... R1 of about 250k). Programming Turn-On and Turn-Off Thresholds with the RUN Pin The LTC1871-7 contains an independent, micropower volt- age reference and comparator detection circuit that remains active even when the device is shut down, as shown in Figure 8. This allows users to accurately program an input voltage at which the converter will turn on and off ...

Page 13

... APPLICATIONS INFORMATION Application Circuits A basic LTC1871-7 application circuit is shown in Figure 9. External component selection is driven by the characteris- tics of the load and the input supply. The fi rst topology to be analyzed will be the boost converter, followed by SEPIC (single-ended primary inductance converter). Boost Converter: Duty Cycle Considerations ...

Page 14

... For a current mode boost regulator operating in CCM, slope compensation must be added for duty cycles above 50% in order to avoid subharmonic oscillation. For the LTC1871-7, this ramp compensation is internal. Having an internally fi xed ramp compensation waveform, however, does place some constraints on the value of the inductor and the operating frequency. If too large an inductor is used, the resulting current ramp (Δ ...

Page 15

... TH(JC) TH(JA) The gate drive voltage is set by the 7V INTV regulator. Consequently, 6V rated MOSFETs are required in most high voltage LTC1871-7 applications. Pay close attention to the BV . The relationship MOSFETs relative to the maximum actual switch voltage in the application. The switch node can ring during the turn-off of the MOSFET due to layout parasitics. Check the ...

Page 16

... LTC1871-7 APPLICATIONS INFORMATION 2.0 1.5 1.0 0.5 0 – JUNCTION TEMPERATURE (°C) Figure 12. Normalized R DS(ON) From a known power dissipated in the power MOSFET, its junction temperature can be obtained using the following formula • FET TH(JA) The used in this equation normally includes TH(JA) the R for the device plus the thermal resistance from ...

Page 17

... A low ESR capacitor is recommended, although it is not as critical as for the output capacitor. The RMS input capacitor ripple current for a boost con- verter is: V IN(MIN) = 0.3 • I • D RMS(CIN) MAX L • f LTC1871-7 V OUT RINGING DUE TO TOTAL INDUCTANCE (BOARD + CAP) 18717 F13 ...

Page 18

... Be sure to specify surge-tested capacitors! Burst Mode Operation and Considerations The choice of sense resistor and inductor value also deter- mines the load current at which the LTC1871-7 enters Burst Mode operation. When bursting, the controller clamps the peak inductor current to approximately: 30mV ...

Page 19

... Although all dissipative elements in the circuit produce losses, four main sources usually account for the majority of the losses in LTC1871-7 application circuits: 1. The supply current into V . The V IN ...

Page 20

... LTC1871-7 APPLICATIONS INFORMATION Checking Transient Response The regulator loop response can be verifi looking at the load transient response at minimum and maximum V . Switching regulators generally take several cycles to IN respond to an instantaneous step in resistive load current. When the load step occurs, V ...

Page 21

... DS(ON) V OUT 1V/DIV I L 2A/DIV MOSFET DRAIN VOLTAGE 20V/DIV 14μF I OUT V OUT D = 81% Figure 15. Switching Waveforms for the Converter in Figure 9 at Minimum V = LTC1871-7 18717 F15 = 8V 1μs/DIV = 0.5A = 42V (8V) IN 18717fc 21 ...

Page 22

... Figure 16. Switching Waveforms for the Converter in Figure 9 at Maximum V PC Board Layout Checklist 1. In order to minimize switching noise and improve out- put load regulation, the GND pin of the LTC1871-7 should be connected directly to 1) the negative terminal of the INTV decoupling capacitor, 2) the negative terminal of ...

Page 23

... For optimum load regulation and true remote sens- ing, the top of the output resistor divider should connect independently to the top of the output capacitor (Kelvin connection), staying away from any high dV/dt traces. Place the divider resistors near the LTC1871-7 in order to keep the high impedance FB node short. JUMPER C ...

Page 24

... For applications with multiple switching power convert- ers connected to the same input supply, make sure that the input fi lter capacitor for the LTC1871-7 is not shared with other converters. AC input current from another converter could cause substantial input voltage ripple, and this could interfere with the operation of the LTC1871-7. A few inches of PC trace or wire (L ≈ ...

Page 25

... The maximum duty cycle of the LTC1871-7 is typically 92%. SEPIC Converter: The Peak and Average Input Currents The control circuit in the LTC1871-7 is measuring the input current (using a sense resistor in the MOSFET source), so the output current needs to be refl ected back to the input in order to dimension the power MOSFET properly. ...

Page 26

... TH(JC) TH(JA) The gate drive voltage is set by the 7V INTV regulator. Consequently, 6V rated threshold MOSFETs are required in most LTC1871-7 applications. The maximum voltage that the MOSFET switch must sustain during the off-time in a SEPIC converter is equal to the sum of the input and output voltages ( result, careful attention must be paid to the BV specifi ...

Page 27

... ESR ceramic capacitor can minimize the ESR step, while an electrolytic or tantalum capacitor can be used to supply the required bulk C. Once the output capacitor ESR and bulk capacitance have been determined, the overall ripple voltage waveform LTC1871-7 0.01• D(PEAK) ...

Page 28

... LTC1871-7 APPLICATIONS INFORMATION should be verifi dedicated PC board (see Board Layout section for more information on component place- ment). Lab breadboards generally suffer from excessive series inductance (due to inter-component wiring), and these parasitics can make the switching waveforms look signifi cantly worse than they would properly designed PC board ...

Page 29

... GATE LTC1871-7 10 SENSE 4.7μF 8 INTV CC 6 GND = 5V OUT 18717 TA02b LTC1871-7 UPS840 V OUT 3.3V • 3A MAX 100μF T1B 6.3V • ×3 Q1 FDC2512 ALL CAPACITORS ARE CERAMIC R3 X5R TYPE 0.1Ω 18717 TA02a Output Effi ciency at 5V Output 90 36V ...

Page 30

... C7 3.3μ 50V 75Ω 10V 100pF 4 200V RUN SENSE LTC1871 INTV FREQ GATE Si4482DY 6 MODE/SYNC GND R13 C15 0.082Ω 4.7μF C16 10nF 1kV ISO1 MOC207 D3 IRF12CW10 TO LEDS C7 10μF 100V Q3 R9 ...

Page 31

... Plastic MSOP (Reference LTC DWG # 05-08-1661) DETAIL “A” 0.254 (.010) 0° – 6° TYP GAUGE PLANE 0.53 ± 0.152 (.021 ± .006) DETAIL “A” 0.18 (.007) LTC1871-7 C52 L7 CR22 4.7μF 150Ω 3A 1N4148 X7R BEAD 1B ×2 (OPTIONAL HF FILTER) CR21 MBR10100 ...

Page 32

... Q1 X7R D1 9. 31.8V 10Ω – = 29.5V RUN SENSE LTC1871-7 FB INTV CC FREQ GATE MODE/SYNC GND 200kHz 4.7μF X5R D1: ON SEMICONDUCTOR MMBZ5239BLT1 (9.1V) D2: ON SEMICONDUCTOR MMSD4148T11 D3: INTERNATIONAL RECTIFIER 10BQ060 COMMENTS 300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology SO-8; 300kHz Operating Frequency; Buck, Boost, SEPIC Design; ...

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