LTC1840 LINER [Linear Technology], LTC1840 Datasheet - Page 8

• Manufacturer Part Number: LTC1840
• Description: Dual Fan Controller with 2-Wire Interface
• Manufacturer: LINER [Linear Technology]

OPERATIO
LTC1840
LTC1840 Device Addressing
It is possible to configure the part to operate with any one
of nine separate addresses through the three state A0 and
A1 pins. Table 1 shows the correspondence of addresses
to the states of the pins:
Table 1. Device Addressing
For the A0 and A1 lines, L refers to a grounded pin, H is a
pin shorted to V
will be set to approximately V
Bits B7, B6 and B5 of the address are hardwired to 111.
Table 2. LTC1840 Register Address and Contents
FAULT
STATUS
DACA
DACB
TACHA
TACHB
GPIO Data
GPIO Setup
Note 1: Number in ( )signifies default bit status upon power-up.
8
Register
Name
(R/W)
Device Address
NC
NC
NC
A0
H
H
H
L
L
L
LTC1840
R2 R1 R0
Register
NC
NC
NC
Address
A1
H
H
H
L
L
L
000
001
010
011
100
101
110
111
CC
U
and NC is no connect. The pin voltage
TACHA FLTEN TACHB FLTEN
GPIO4 BLNK
B4
TACHA FLT
GPIO4 Pin
0
0
0
0
0
0
0
0
1
Cnt A7
Cnt B7
(N/A)
MSB
MSB
2-Wire Bus Slave Address Bits
(0)
(0)
(0)
(0)
(1)
(1)
(0)
D7
CC
(B7,B6,B5 = 111)
B3
0
0
0
0
1
1
1
1
0
/2 when not connected.
GPIO3 BLNK
TACHB FLT
GPIO3 Pin
Cnt A6
Cnt B6
(N/A)
Bit 6
Bit 6
(0)
(0)
(0)
(0)
(1)
(1)
(0)
D6
B2
0
0
1
1
0
0
1
1
0
GPIO2 BLNK
GPIO2 Pin
Cnt A5
Cnt B5
(N/A)
DIV1
Blast
Bit 5
Bit 5
D5
(0)
(0)
(0)
(0)
(1)
(1)
(0)
B1
0
1
0
1
0
1
0
1
0
GPIO1 BLNK
GPIO1 Pin
Register Addresses and Contents
Fault conditions are cleared by the action of writing to the
fault register, but the data byte from the write command is
not actually loaded into the register.
A TACHA/B FLT (fault) bit will be high if the corresponding
TACHA/B FLTEN bit in the status register has been set high
and the corresponding TACHA/B counter has overflowed
its maximum count of 255. These faults are latched
internally and must be cleared by writing to the fault
register or by setting TACHA/B FLTEN low. The fault will be
reasserted if the counter is still in overflow after a write to
the fault register. The TACH FLT bits power-up in the low
state.
The blast and timer bits become high after blasting and
serial access time-out events, respectively.
A high GPIOX FLT bit reflects that the GPIOX pin has
caused a fault condition; to do so, the pin must be enabled
as fault producing in the GPIO setup register (GPIOX
FLTEN set high) and the logic state of the pin must change
after the enable. The fault is latched internally and must be
cleared through software by writing to the fault register or
by setting GPIOX FLTEN low; a change in the state of the
GPIOX pin from its state at the point of the fault register
being written will cause another fault to be signalled.
Note 2: State of bit depends on slave address used.
Cnt A4
Cnt B4
Timer
(N/A)
DIV0
Bit 4
Bit 4
D4
(0)
(0)
(0)
(0)
(1)
(1)
(0)
Data Byte
GPIO4 FLTEN GPIO3 FLTEN GPIO2 FLTEN GPIO1 FLTEN
*See Note 2
GPIO4 Reg
GPI04 FLT
Cnt A3
Cnt B3
(0/1)
Bit 3
Bit 3
(0)
(0)
(0)
(1)
(1)
(1)
(0)
D3
GPIO3 Reg
GPI03 FLT
Cnt A2
Cnt B2
Bit 2
Bit 2
D2
(0)
(0)
(0)
(0)
(1)
(1)
(1)
(0)
GPIO2 Reg
GPI02 FLT
Cnt A1
Cnt B1
Bit 1
Bit 1
D1
(0)
(0)
(0)
(0)
(1)
(1)
(1)
(0)
GPIO1 Reg
GPI01 FLT
Cnt A0
Cnt B0
LSB
LSB
(0)
(1)
(0)
(0)
(1)
(1)
(1)
(0)
D0
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