LTC1771 LINER [Linear Technology], LTC1771 Datasheet - Page 10

• Manufacturer Part Number: LTC1771
• Description: Low Quiescent Current High Efficiency Step-Down DC/DC Controller
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC1771
Minimum On-Time Considerations
Minimum on-time t
that the LTC1771 is capable of turning the top MOSFET on
and off again. It is determined by internal timing delays and
the amount of gate charge required to turn on the
P-channel MOSFET. Low duty cycle applications may
approach this minimum on-time limit and care should be
taken to ensure that:
where t
for the LTC1771.
If the duty cycle falls below what can be accommodated by
the minimum on-time, the LTC1771 will remain in Burst
Mode operation even at high load currents. The output
voltage will continue to be regulated, but the ripple current
and ripple voltage will increase.
Mode Pin
Burst Mode operation is disabled by pulling MODE (Pin 8)
below 0.5V. Disabling Burst Mode operation provides a
low noise output spectrum, useful for reducing both audio
and RF interference. It does this by keeping the frequency
constant (for fixed V
(1% to 2% of I
voltage and current ripple at light loads. When Burst Mode
operation is disabled, efficiency is reduced at light loads
and no load supply current increases to 175 A.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC1771. These items are also illustrated graphically in
the layout diagram of Figure 3. Check the following in your
layout:
10
t
ON
OFF
t
OFF
= 3.5 s and t
V
V
MAX
OUT
IN
ON(MIN)
) and reducing the amount of output
U
IN
V
) down to much lower load current
OUT
V
D
ON(MIN)
U
is the smallest amount of time
t
ON MIN
is generally about 0.5 s
(
W
)
U
1. Is the Schottky diode closely connected to the drain of
2. Is the 0.1 F input decoupling capacitor closely con-
3. Does the V
4. Is the 1000pF decoupling capacitor for the current
5. Is the (+) plate of C
6. Are the signal and power grounds segregated? The
7. Keep the switching node (SW) and the gate node
8. High impedance nodes such as I
the external MOSFET and the input cap ground?
nected between V
capacitor carries the high frequency peak currents.
resistors? The resistive divider R1 and R2 must be
connected between the (+) plate of C
ground. Locate the feedback resistors right next to the
LTC1771. The V
nodes with high slew rates.
sense resistor connected as close as possible to Pins 6
and 7? Ensure accurate current sensing with Kelvin
connections to the sense resistor.
resistor ? This capacitor provides the AC current to the
MOSFET.
signal ground consists of the (–) plate of C
the LTC1771 and the resistive divider. The power ground
consists of the Schottky diode anode and the (–) plate
of C
possible.
(PGATE) away from sensitive small signal nodes, espe-
cially the voltage sensing feedback pin (V
mize their PC trace area.
sensitive to leakage paths on the PC board due to stray
flux, solder, epoxy, etc. Make sure PC board is clean.
Water-soluble solder flux can be especially leaky if not
cleaned properly. Leakage on I
excessive output ripple during Burst Mode operation. If
the problem persists, adding a 10M resistor from Pin 2
to ground should eliminate the problem.
IN
which should have as short lead lengths as
FB
pin connect directly to the feedback
FB
IN
line should not be routed close to any
IN
(Pin 6) and ground (Pin 4)? This
closely connected to the sense
TH
will manifest itself as
TH
and V
OUT
FB
OUT
), and mini-
FB
and signal
, Pin 4 of
are very