LTC1669 LINER [Linear Technology], LTC1669 Datasheet - Page 5

• Manufacturer Part Number: LTC1669
• Description: 10-Bit Rail-to-Rail Micropower DAC with I2C Interface
• Manufacturer: LINER [Linear Technology]

PIN
DEFINITIONS
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
Where V
two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Full-Scale Error (FSE): The deviation of the actual full-
scale voltage from ideal. FSE includes the effects of offset
and gain errors (see Applications Information).
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code that guarantees the output will be greater than
SDA (Pin 1, Pin 1 on SOT-23): Serial Data Bidirectional
Pin. Data is shifted into the SDA pin and acknowledged by
the SDA pin. High impedance pin while data is shifted in.
Open-drain N-channel output during acknowledgment.
Requires a pull-up resistor or current source to V
AD1 (Pin 2): Slave Address Select Bit 1. Tie this pin to
either V
LTC1669’s slave address.
AD2 (Pin 3): Slave Address Select Bit 2. Tie this pin to
either V
LTC1669’s slave address.
SCL (Pin 4, Pin 5 on SOT-23): Serial Clock Input Pin. Data
is shifted into the SDA pin at the rising edges of the clock.
This high impedance pin requires a pull-up resistor or
current source to V
DNL = ( V
U
FUNCTIONS
U
CC
CC
OUT
or GND to modify the corresponding bit of the
or GND to modify the corresponding bit of the
U
OUT
is the measured voltage difference between
U
– LSB)/LSB
CC
U
.
CC
.
V
part is programmed to use V
AD0 (Pin 6): Slave Address Select Bit 0. Tie this pin to
either V
LTC1669’s slave address.
GND (Pin 7, Pin 2 on SOT-23): System Ground.
V
rail-to-rail DAC output.
zero. The INL error at a given input code is calculated as
follows:
Where V
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
Resolution (n): Defines the number of DAC output states
(2
imply linearity.
Voltage Offset Error (V
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
CC
OUT
5.5V. Also used as the reference voltage input when the
n
INL = [V
LSB = V
) that divide the full-scale range. Resolution does not
(Pin 5, Pin 4 on SOT-23): Power Supply. 2.7V V
(Pin 8, Pin 3 on SOT-23): Voltage Output. Buffered
CC
OUT
or GND to modify the corresponding bit of the
REF
OUT
is the output voltage of the DAC measured at
/1024
– V
OS
– (V
OS
): Nominally, the voltage at the
FS
– V
CC
as the reference.
OS
)(code/1023)]/LSB
LTC1669
5
1669f
CC