LTC1654 LINER [Linear Technology], LTC1654 Datasheet - Page 4

• Manufacturer Part Number: LTC1654
• Description: Dual 14-Bit Rail-to-Rail DAC in 16-Lead SSOP Package
• Manufacturer: LINER [Linear Technology]

PI FU CTIO S
TI I G DIAGRA S
LTC1654
ELECTRICAL CHARACTERISTICS
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Nonlinearity is defined from code 50 to code 16383 (full scale).
See Applications Information.
Note 3: 100pF Load Capacitor
Note 4: DAC switched between code 200 and code 16383.
X
1/2 Pin. When this pin is tied to V
up to REFHI/2 and when this pin is tied to REFLO, the
output will swing up to REFHI. These pins should not be
left floating.
CLR (Pin 2): The Asynchronous Clear Input.
SCK (Pin 3): The TTL Level Input for the Serial Interface
Clock.
SDI (Pin 4): The TTL Level Input for the Serial Interface
Data. Data on the SDI pin is latched into the shift register
on the rising edge of the serial clock. The LTC1654 re-
quires a 24-bit word. The first 8 bits are control/address
followed by 16 data bits. The last two of the 16 data bits are
don’t cares. If daisy-chaining is desired, then a 32-bit data
word can be used with the first 8 being don’t cares and the
following 24 bits as above.
CS/LD (Pin 5): The TTL Level Input for the Serial Interface
Enable and Load Control. When CS/LD is low, the SCK
4
1
/X
W
U
1/2
U
B, X
U
1
/X
1/2
A (Pins 1, 8): The Gain of 1 or Gain of
U
W
CS/LD
SDO
SCK
SDI
OUT
(PREVIOUS
, the output will swing
WORD)
X
t
1
X
t
2
X
t
8
X
C3
t
4
C3
Note 5: Digital inputs at 0V or V
Note 6: Guaranteed by design.
Note 7: V
when output is unloaded. See Applications Information.
Note 8: CS/LD = 0, V
signal is enabled, so the data can be clocked in. When
CS/LD is pulled high, the control/address bits are
decoded.
DGND/AGND (Pins 6, 12): Digital and Analog Grounds.
SDO (Pin 7): The output of the shift register that becomes
valid on the rising edge of the serial clock.
V
REFHI A/B (Pins 10, 14): The Reference High Inputs of the
LTC1654. There is a gain of 1 from this pin to the output
in a gain of 1 configuration. In a gain of 1/2 configuration,
there is a gain of 1/2 from this pin to V
REFLO A/B (Pins 11, 13): The Reference Low Inputs of the
LTC1654.
V
Requires a 0.1 F bypass capacitor to ground.
B0
OUT A/B
CC
X
(Pin 16): The Positive Supply Input. 2.7V V
t
X
OUT
3
(Pins 9, 15): The Buffered DAC Outputs.
can only swing from (GND + V
X
t
6
X
OUT
t
CURRENT WORD
5
t
9
= 4.096 and data is being clocked in.
t
7
X
CC
1654 TD01
.
OS
) to (V
OUT
CC
.
– V
CC
OS
)
5.5V.