LTC1456 LINER [Linear Technology], LTC1456 Datasheet - Page 5

• Manufacturer Part Number: LTC1456
• Description: 12-Bit Rail-to-Rail Micropower DAC with Clear Input
• Manufacturer: LINER [Linear Technology]

CLK (Pin 1): The Serial Interface Clock. Internal Schmitt
trigger on this input allows direct optocoupler interface.
D
is latched into the shift register on the rising edge of the
serial clock.
CS/LD (Pin 3): The Serial Interface Enable and Load
Control. When CS/LD is low the CLK signal is enabled, so
the data can be clocked in. When CS/LD is pulled high,
data is loaded from the shift register into the DAC
register, updating the DAC output. When CS/LD is high
the CLK is disabled internally.
TI I G DIAGRA
PIN
BLOCK
IN
W U
U
(Pin 2): The Serial Interface Data. Data on the D
FUNCTIONS
CS/LD
D
OUT
CLK
D
U
IN
I D AGRA
CS/LD
PREVIOUS WORD
D
CLK 1
OUT
D
IN
U
2
B0
3
4
t
W
9
W
PREVIOUS WORD
B11
REGISTER
12-BIT
SHIFT
t
1
POWER-ON
RESET
MSB
B11
t
2
REGISTER
DAC
B10
LD
IN
pin
t
8
B10
D
Becomes Valid on the Rising Edge of the Serial Clock.
GND (Pin 5): Ground.
CLR (Pin 6): The Clear Input. When pulled low, this pin
asynchronously clears the internal shift and DAC registers
to zero scale. Should be tied high for normal operation.
V
V
Requires a bypass capacitor to ground.
2.048V
12-BIT
t
OUT
CC
DAC
OUT
4
(Pin 8): The Positive Supply Input. 4.5V V
(Pin 7): The Buffered DAC Output.
(Pin 4): The Output of the Shift Register Which
B1
–
+
B1
t
3
B0
t
6
8
7
6
5
LSB
1146 BD
B0
V
V
CLR
GND
CURRENT WORD
OUT
CC
t
5
B11
t
7
1456 TD
LTC1456
CC
5.5V.
5