LTC1418 LINER [Linear Technology], LTC1418 Datasheet - Page 25

• Manufacturer Part Number: LTC1418
• Description: Low Power, 14-Bit, 200ksps ADC with Serial and Parallel I/O
• Manufacturer: LINER [Linear Technology]

APPLICATIONS
also allows operation when the SCLK frequency is very low
(less than 30kHz). To select the internal conversion clock
tie EXT/INT low. The external SCLK is applied to SCLK. RD
can be used to gate the external SCLK, such that data will
clock only after RD goes low and to three-state D
data transfer. If more than 16 SCLKs are provided, more
zeros will be filled in after the data word indefinitely.
CS = 0, EXT/INT = 5
EXTCLKIN
CONVST
BUSY
D
SCLK
OUT
RD
t
t
dEXTCLKIN
6
U
t
5
1
Figure 25. External Conversion Clock Selected. Data Transferred After Conversion
Using an External SCLK. BUSY Indicates End of Conversion
2
(SAMPLE N)
INFORMATION
U
3
4
5
HOLD
6
CONVST
t
CONV
W
7
Hi-Z
8
9 10 11 12 13 14 15 16
24
CONVST
U
OUT
LTC1418
CS
EXTCLKIN
25
after
EXT/INT
BUSY
SCLK
D
OUT
RD
t
7
26
19
20
16
23
17
Using External Conversion Clock and External Data
Clock. In Figure 25, data is also output after each conver-
sion is completed and before the next conversion is
started. An external clock is used for the conversion clock
and either another or the same external clock is used for
the SCLK. This mode is identical to Figure 24 except that
an external clock is used for the conversion. This mode
5V
D13
t
9
1
t
13
t
10
12 11 10 9
2
3
4
SCLK
D
5
OUT
DATA N
CLKOUT
INT
C0
SCK
MISO
8
6
P OR DSP
7
7
1418 F25a
t
6
V
8
8
SAMPLE
IL
D13
5
9 10 11 12 13 14 15 16
t
15
4
t
t
14
LSCLK
3
RISING CLOCK
CAPTURE ON
2
1
0
D12
t
HSCLK
ZEROS
FILL
FALLING CLOCK
CAPTURE ON
LTC1418
t
11
1418 F25b
Hi-Z
D11
1
25
2
V
V
OH
OL
3 4