LTC1407 LINER [Linear Technology], LTC1407 Datasheet - Page 16

• Manufacturer Part Number: LTC1407
• Description: Serial 12-Bit/14-Bit, 3Msps Simultaneous Sampling Simultaneous Sampling
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC1407/LTC1407A
DIGITAL INTERFACE
The LTC1407/LTC1407A have a 3-wire SPI (Serial Proto-
col Interface) interface. The SCK and CONV inputs and
SDO output implement this interface. The SCK and CONV
inputs accept swings from 3V logic and are TTL compat-
ible, if the logic swing does not exceed V
description of the three serial port signals follows:
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subse-
quent rising edges at CONV are ignored by the LTC1407/
LTC1407A until the following 32 SCK rising edges have
occurred. The duty cycle of CONV can be arbitrarily chosen
to be used as a frame sync signal for the processor serial
port. A simple approach to generate CONV is to create a
pulse that is one SCK wide to drive the LTC1407/LTC1407A
and then buffer this signal to drive the frame sync input of
the processor serial port. It is good practice to drive the
LTC1407/LTC1407A CONV input first to avoid digital noise
interference during the sample-to-hold transition trig-
gered by CONV at the start of conversion. It is also good
practice to keep the width of the low portion of the CONV
signal greater than 15ns to avoid introducing glitches in
the front end of the ADC just before the sample-and-hold
goes into Hold mode at the rising edge of CONV.
Minimizing Jitter on the CONV Input
In high speed applications where high amplitude sinewaves
above 100kHz are sampled, the CONV signal must have as
little jitter as possible (10ps or less). The square wave
output of a common crystal clock module usually meets
this requirement easily. The challenge is to generate a
CONV signal from this crystal clock without jitter corrup-
tion from other digital circuits in the system. A clock
divider and any gates in the signal path from the crystal
clock to the CONV input should not share the same
integrated circuit with other parts of the system. As shown
in the interface circuit examples, the SCK and CONV inputs
should be driven first, with digital buffers used to drive the
serial port interface. Also note that the master clock in the
DSP may already be corrupted with jitter, even if it comes
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directly from the DSP crystal. Another problem with high
speed processor clocks is that they often use a low cost,
low speed crystal (i.e., 10MHz) to generate a fast, but
jittery, phase-locked-loop system clock (i.e., 40MHz). The
jitter in these PLL-generated high speed clocks can be
several nanoseconds. Note that if you choose to use the
frame sync signal generated by the DSP port, this signal
will have the same jitter of the DSP’s master clock.
Serial Clock Input (SCK)
The rising edge of SCK advances the conversion process
and also udpates each bit in the SDO data stream. After
CONV rises, the third rising edge of SCK sends out two
sets of 12/14 data bits, with the MSB sent first. A simple
approach is to generate SCK to drive the LTC1407/
LTC1407A first and then buffer this signal with the appro-
priate number of inverters to drive the serial clock input of
the processor serial port. Use the falling edge of the clock
to latch data from the Serial Data Output (SDO) into your
processor serial port. The 14-bit Serial Data will be re-
ceived right justified, in two 16-bit words with 32 or more
clocks per frame sync. It is good practice to drive the
LTC1407/LTC1407A SCK input first to avoid digital noise
interference during the internal bit comparison decision
by the internal high speed comparator. Unlike the CONV
input, the SCK input is not sensitive to jitter because the
input signal is already sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends
out two sets of 12/14 bits in the output data stream after
the third rising edge of SCK after the start of conversion
with the rising edge of CONV. The two 12-/14-bit words are
separated by two clock cycles in high impedance mode.
Please note the delay specification from SCK to a valid
SDO. SDO is always guaranteed to be valid by the next
rising edge of SCK. The 32-bit output data stream is
compatible with the 16-bit or 32-bit serial port of most
processors.
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