ICM7321 ICMIC [IC MICROSYSTEMS], ICM7321 Datasheet - Page 6

• Manufacturer Part Number: ICM7321
• Description: SINGLE 12/10/8-BIT VOLTAGE-OUTPUT DACS
• Manufacturer: ICMIC [IC MICROSYSTEMS]

The ICM7361 is a 12-bit voltage output DAC. The
ICM7341 is the 10-bit version of this family and the
ICM7321 is the 8-bit version.
This family of DACs has guaranteed monotonic behavior.
There is a 1.25V onboard reference and an operating
supply range of 2.7V to 5.5V.
There is an internal bandgap reference of 1.25V on these
parts and there is a gain of two in the output amplifiers
which means they swing from ground at code 0 to 2.5V at
full-scale :
Where D=digital input (decimal) and n= number of bits, i.e.
12 for ICM7361, 10 for ICM7341 and 8 for ICM7321.
The reference output is nominally 1.25V and is brought out
to a separate pin, REFOUT (8-pin MSOP package only)
and can be used to drive external loads. However, it is still
internally connected to the DAC reference input. The
outputs will nominally swing from 0 to 2.5V.
The DAC has an output amplifier with a wide output
voltage swing. The actual swing of the output amplifier will
be limited by offset error and gain error. See the
Applications Information Section for a more detailed
discussion.
The amplifier is configured in a gain of 2 with internal gain
resistors of about 50 k . The output swing will be from 0V
to 2.5V at full-scale.
The output amplifier can drive a load of 2.0 k
GND in parallel with a 500 pF load capacitance.
The output amplifier has a full-scale typical settling time of
8
voltage.
This DAC family uses a standard 3-wire connection
compatible with SPI/QSPI interfaces. Data is loaded in 16-
bit words which consist of 4 address and control bits
(MSBs) followed by 12 bits of data (see table 1). The
ICM7341 has the last two LSBs as don’t cares and the
ICM7321 has the last 4 LSBs as don’t cares. The DAC is
double buffered with an input latch and a DAC latch.
All the digital inputs are CMOS/TTL compatible. The
current dissipation of the device however, will be higher
when the inputs are driven at TTL levels.
Data is clocked in on the rising edge of SCK which has a
Schmitt trigger internally to allow for noise immunity on the
SCK pin. This specially eases the use for opto-coupled
interfaces.
The CS pin must be low when data is being clocked into
the part. After the 16
pulled high (level-triggered) for the data to be transferred
to an input bank of latches. The CS pin also disables the
SCK pin internally when pulled high and the SCK pin must
be low before the CS pin is pulled back low. As the CS pin
is pulled high the shift register contents are transferred to
a bank of 16 latches. The 4 bit control word (C3~C0) is
Rev. A8
s and it dissipates about 100
Vout = 2 x (1.25 xD)/2
th
clock pulse the CS pin must be
n
ICmic reserves the right to change the specifications without prior notice.
A with a 3V supply
to V
DD
or
then decoded and the DAC is updated or loaded
depending on the control word (see Table 1).
The DAC has a double-buffered input with an input latch
and a DAC latch. The DAC output will swing to its new
value when data is loaded into the DAC latch. The user
has three options: loading only the input latch, updating
the DAC with data previously loaded into the input latch or
loading the input latch and updating the DAC at the same
time with a new code.
There is a power-on reset on board that will clear the
contents of all the latches to all 0s on power-up and the
DAC voltage output will go to ground.
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