LTAEY LINEAR [Linear Integrated Systems], LTAEY Datasheet - Page 17

• Manufacturer Part Number: LTAEY
• Description: Differential Input 16-Bit No Latency DS ADC
• Manufacturer: LINEAR [Linear Integrated Systems]

APPLICATIO S I FOR ATIO
disabled. Hence, SCK remains LOW. On the next falling
edge of CS, the device is switched to the external SCK
timing mode. By adding an external 10k pull-up resistor to
SCK, this pin goes HIGH once the external driver goes
Hi-Z. On the next CS falling edge, the device will remain in
the internal SCK timing mode.
A similar situation may occur during the sleep state when
CS is pulsed HIGH-LOW-HIGH in order to test the
conversion status. If the device is in the sleep state (EOC
= 0), SCK will go LOW. Once CS goes HIGH (within the time
period defined above as t
activated. For a heavy capacitive load on the SCK pin, the
internal pull-up may not be adequate to return SCK to a
HIGH level before CS goes low again. This is not a concern
under normal conditions where CS remains LOW after
detecting EOC = 0. This situation is easily overcome by
adding an external 10k pull-up resistor to the SCK pin.
(INTERNAL)
SDO
SCK
SLEEP
CS
Hi-Z
> t
OUTPUT
DATA
EOCtest
BIT 0
EOC
U
CONVERSION
Hi-Z
TEST EOC
U
EOCtest
Hi-Z
Figure 10. Internal Serial Clock, Reduced Data Output Length
), the internal pull-up is
SLEEP
(OPTIONAL)
W
TEST EOC
SLEEP
ANALOG INPUT RANGE
Hi-Z
–0.5V
<t
EOCtest
REF
U
BIT 18
0.1V TO V
REFERENCE
EOC
TO 0.5V
VOLTAGE
1 F
2.7V TO 5.5V
REF
CC
BIT 17
“O”
1
2
3
4
5
6
V
REF
REF
IN
IN
GND
CC
Internal Serial Clock, 2-Wire I/O,
Continuous Conversion
This timing mode uses a 2-wire, all output (SCK and SDO)
interface. The conversion result is shifted out of the device
by an internally generated serial clock (SCK) signal, see
Figure 11. CS may be permanently tied to ground, simpli-
fying the user interface or isolation barrier.
The internal serial clock mode is selected at the end of the
power-on reset (POR) cycle. The POR cycle is concluded
approximately 1ms after V
pull-up is active during the POR cycle; therefore, the
internal serial clock timing mode is automatically selected
if SCK is not externally driven LOW (if SCK is loaded such
that the internal pull-up cannot pull the pin HIGH, the
external SCK mode will be selected).
LTC2433-1
+
–
+
–
BIT 16
SIG
SDO
SCK
CS
F
O
10
9
8
7
DATA OUTPUT
BIT 15
MSB
3-WIRE
SPI INTERFACE
BIT 14
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
BIT 13
CC
exceeds 2V. An internal weak
BIT 2
LTC2433-1
V
CC
CONVERSION
10k
Hi-Z
TEST EOC
17
24331 F10
24331fa