IRS2453D IRF [International Rectifier], IRS2453D Datasheet - Page 9

• Manufacturer Part Number: IRS2453D
• Description: SELF-OSCILLATING FULL-BRIDGE DRIVER IC
• Manufacturer: IRF [International Rectifier]

Functional Description
Under-voltage Lock-Out Mode (UVLO)
The under-voltage lockout mode (UVLO) is defined as the state
the IC is in when VCC is below the turn-on threshold of the IC.
The IRS2453D under voltage lock-out is designed to maintain an
ultra low supply current of less than 150uA, and to guarantee the
IC is fully functional before the high and low side output drivers
are activated. During under voltage lock-out mode, the high and
low-side driver outputs LO1, LO2, HO1, HO2 are all low. With
VCC above the VCCUV+ threshold, the IC turns on and the
output begin to oscillate.
Normal operating mode
Once VCC reaches the start-up threshold VCCUV+, the
MOSFET M1 opens, RT increases to approximately VCC (VCC-
VRT+) and the external CT capacitor starts charging. Once the
CT voltage reaches VCT- (about 1/3 of VCC), established by an
internal resistor ladder, LO1 and HO2 turn on with a delay
equivalent to the deadtime td. Once the CT voltage reaches
VCT+ (approximately 2/3 of VCC), LO1 and HO2 go low, RT
goes down to approximately ground (VRT-), the CT capacitor
starts discharging and the deadtime circuit is activated. At the
end of the deadtime, LO2 and HO1 go high. Once the CT voltage
reaches VCT-, LO2 and HO1 go low, RT goes to high again, the
deadtime is activated. At the end of the deadtime, LO1 and HO2
go high and the cycle starts over again.
The frequency is best determined by the graph, Frequency vs.
RT, Page 3, for different values of CT. A first order approximate
of the oscillator frequency can also be calculated by the following
formula::
This equation can vary slightly from actual measurements due to
internal comparator over- and under-shoot delays.
Bootstrap MOSFET
The internal bootstrap FET and supply capacitor (C
comprise the supply voltage for the high side driver circuitry. The
internal boostrap FET only turns on when the corresponding LO
is high. To guarantee that the high-side supply is charged up
before the first pulse on HO1 and HO2, LO1 and LO2 are both on
when CT ramps between zero and 1/3*VCC. LO1 and LO2 are
also on when CT is grounded below 1/6*VCC to ensure that the
bootstrap capacitor is charged when CT is brought back over
1/3*VCC.
Non-latched Shutdown
If CT is pulled down below V CTSD (approximately 1/6 of VCC) by
an external circuit, CT doesn’t charge up and oscillation stops. All
outputs are held low and the bootstrap FETs are off. Oscillation
will resume once CT is able to charge up again to VCT-.
f
≈
. 1
453
×
1
RT
×
CT
BOOT
)
Latched Shutdown
When the SD pin is brought above 2V, the IC goes into fault
mode and all outputs are low. VCC has to be recycled below
VCCUV- to restart the IC. The SD pin can be used for over-
current or over-voltage protection using appropriate external
circuitry.
HO1
HO
LO1
LO
Rise and fall time waveform
Deadtime Waveform Definitions
Deadtime waveform
td_HO1
tr
50%
50%
90%
10%
50%
50%
td_LO1
IRS2453DPbF
ton_LO
tf
50%
9