C501G-1E SIEMENS [Siemens Semiconductor Group], C501G-1E Datasheet - Page 30

• Manufacturer Part Number: C501G-1E
• Description: 8-Bit Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

4.1.2 Timing
The timing of the external bus interface, in particular the relationship between the control signals
ALE, PSEN, RD, WR and information on port 0 and port 2, is illustated in figure 4-1 a) and b).
Data memory:
Program memory: Signal PSEN functions as a read strobe.
4.1.3 External Program Memory Access
The external program memory is accessed under two conditions:
This requires the ROM-less version C501-L to have EA wired low to allow the lower 8K program
bytes to be fetched from external memory.
When the CPU is executing out of external program memory, all 8 bits of port 2 are dedicated to an
output function and may not be used for general-purpose I/O. The contents of the port 2 SFR
however is not affected. During external program memory fetches port 2 lines output the high byte
of the PC, and during accesses to external data memory they output either DPH or the port 2 SFR
(depending on whether the external data memory access is a MOVX @DPTR or a MOVX @Ri).
When the C501 executes instructions from external program memory, port 2 is at all times
dedicated to output the high-order address byte. This means that port 0 and port 2 of the C501 can
never be used as general-purpose I/O. This means that port 0 and port 2 of the C501-L can never
be used as general-purpose I/O. This also applies to the C501-1R/1E when they are operating with
external program memory only.
Semiconductor Group
– whenever signal EA is active (low) or
– whenever the program counter (PC) contains a number that is larger than 1FFF H .
in a write cycle, the data byte to be written appears on port 0 just before WR is
activated and remains there until after WR is deactivated. In a read cycle, the
incoming byte is accepted at port 0 before the read strobe is deactivated.
4-3
External Bus Interface
C501