AD5412ACPZ AD [Analog Devices], AD5412ACPZ Datasheet
AD5412ACPZ
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AD5412ACPZ Summary of contents
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Preliminary Technical Data FEATURES 12/16-Bit Resolution and Monotonicity Current Output Ranges: 4–20mA, 0–20mA or 0–24mA 0.1% typ Total Unadjusted Error (TUE) 5ppm/°C Output Drift Voltage Output Ranges: 0-5V, 0-10V, ±5V, ±10V, 10% over-range 0.05% Total Unadjusted Error (TUE) 3ppm/°C Output ...
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AD5412/AD5422 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 AC Performance Characteristics ................................................ 7 Timing Characteristics ................................................................ 8 Absolute Maximum Ratings.......................................................... 10 ESD Caution................................................................................ 10 ...
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Preliminary Technical Data FUNCTIONAL BLOCK DIAGRAM SELECT AD5412/AD5422 CLEA R SELECT CLEA R INPUT SHIFT LATCH REGISTER SCLK AND SDIN CONTROL SDO LOGIC POWER ON RESET DGND* *LFCSP Package CAP1* CAP2* CC 12/16-Bit 16 / DAC VREF ...
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AD5412/AD5422 SPECIFICATIONS AV = 10.8V to 40V -26.4V to -3V/ kΩ OUT L all specifications ±10 V ...
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Preliminary Technical Data Parameter Output Voltage TC Output Voltage Drift vs. Time Short-Circuit Current Load Capacitive Load Stability R = ∞ kΩ ∞ Output Impedance Power-On Time DC PSRR CURRENT OUTPUT ...
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AD5412/AD5422 Parameter Load Current Short Circuit Current 2 Line Regulation 2 Load Regulation Thermal Hysteresis 2 2 DIGITAL INPUTS V , Input High Voltage Input Low Voltage IL Input Current Pin Capacitance 2 DIGITAL OUTPUTS SDO V ...
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Preliminary Technical Data AC PERFORMANCE CHARACTERISTICS AV = 10.8V to 40V -26.4V to -3V/ kΩ OUT L all specifications T to ...
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AD5412/AD5422 TIMING CHARACTERISTICS AV = 10.8V to 40V -26.4V to -3V/ kΩ OUT L all specifications ±10 ...
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Preliminary Technical Data SCLK LATCH SDIN CLEAR OUTPUT SCLK LATCH SDIN DB23 INPUT WORD SPECIFIES REGISTER TO BE READ SDO UNDEFINED DATA SCLK 1 2 LATCH SDIN DB23 INPUT WORD ...
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AD5412/AD5422 ABSOLUTE MAXIMUM RATINGS T = 25°C unless otherwise noted. A Transient currents 100 mA do not cause SCR latch-up. Table 5. Parameter Rating AV to AGND, DGND −0.3V to 48V AGND, DGND +0.3 ...
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Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS FAULT 3 GND 4 CLEAR SELECT 5 CLEAR 6 (Not to Scale) LATCH 7 SCLK 8 SDIN 9 SDO 10 AGND 11 GND 12 Figure 5. ...
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AD5412/AD5422 TSSOP Pin No. LFCSP Pin No. Mnemonic OUT 20 27 BOOST N/A 28 CAP1 N/A 29 CAP2 OUT SENSE SENSE Paddle Paddle AV ...
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Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS VOLTAGE OUTPUT Figure 7. Integral Non Linearity Error vs DAC Code (Four Traces) Figure 8. Differential Non Linearity Error vs. DAC Code (Four Traces) Figure 9. Total Unadjusted Error vs. DAC Code (Four Traces) ...
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AD5412/AD5422 Figure 13.Differential Non Linearity Error vs. Supply Voltage (Four Traces) Figure 14. Integral Non Linearity Error vs. Reference Voltage (Four traces) Figure 15. Differential Non Linearity Error vs. Reference Voltage (Four Traces) Preliminary Technical Data Figure 16. Total Unadjusted ...
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Preliminary Technical Data Figure 19. Bipolar Zero Error vs. Temperature Figure 20. Gain Error vs. Temperature Figure 21. Source and Sink Capability of Output Amplifier Full-Scale Code Loaded Figure 22. Source and Sink Capability of Output Amplifier Zero-Scale Loaded Figure ...
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AD5412/AD5422 Figure 25. Digital-to-Analog Glitch Energy Figure 26. Peak-to-Peak Noise (0.1Hz to 10Hz Bandwidth) Figure 27. Peak-to-Peak Noise (100kHz Bandwidth) Preliminary Technical Data Figure 28. V Figure 29. V OUT Rev. PrF | Page vs. Time on ...
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Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS CURRENT OUTPUT Figure 30. Integral Non Linearity vs. Code Figure 31.Differential Non Linearity vs. Code Figure 32. Total Unadjusted Error vs. Code Figure 33. Integral Non Linearity vs. Temperature Figure 34. Differential Non Linearity ...
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AD5412/AD5422 Figure 36. Differential Non Linearity vs. Supply Voltage Figure 37. Integral Non Linearity vs. Reference Voltage Figure 38. Differential Non Linearity vs. Reference Voltage Preliminary Technical Data Figure 39. Total Unadjusted Error vs. Reference Voltage Figure 40. Total Unadjusted ...
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Preliminary Technical Data Figure 42. Gain Error vs. Temperature Figure 43. Voltage Compliance vs. Temperature Figure 44. I Figure 45. I OUT Rev. PrF | Page AD5412/AD5422 vs. Time on Power-up OUT vs. Time on Output Enabled ...
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AD5412/AD5422 TYPICAL PERFORMANCE CHARACTERISTICS GENERAL Figure 46. DI vs.Logic Input Voltage CC Figure 47 Figure 48 / Rev. PrF | Page Preliminary Technical Data ...
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Preliminary Technical Data Figure 52. Refout Output Noise (100kHz Bandwidth) Figure 53. Refout Line Transient Figure 54. Refout Load Transient Figure 55. Refout Histogram of Thermal Hysteresis Figure 56. Refout Voltage vs. Load Current Rev. PrF | Page 21 of ...
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AD5412/AD5422 TERMINOLOGY Relative Accuracy or Integral Nonlinearity (INL) For the DAC, relative accuracy, or integral nonlinearity (INL measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. A ...
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Preliminary Technical Data Reference measure of the change in the reference output voltage with a change in temperature expressed in ppm/°C. Line Regulation Line regulation is the change in reference output voltage due to a ...
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AD5412/AD5422 THEORY OF OPERATION The AD5412/AD5422 is a precision digital to current loop and voltage output converter designed to meet the requirements of industrial process control applications. It provides a high precision, fully integrated, low cost single-chip solution for generating ...
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Preliminary Technical Data Input Shift Register The input shift register is 24 bits wide. Data is loaded into the device MSB first as a 24-bit word under the control of a serial clock input, SCLK. Data is clocked in on ...
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AD5412/AD5422 Daisy-Chain Operation For systems that contain several devices, the SDO pin can be used to daisy chain the devices together as shown in Figure 60. This daisy-chain mode can be useful in system diagnostics and in reducing the number ...
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Preliminary Technical Data POWER-ON STATE On power-up of the AD5412/AD5422, the power-on-reset circuit ensures that all registers are loaded with zero-code, as such both outputs will be disabled. (V OUT TRANSFER FUNCTION Voltage Output For a unipolar voltage output range, ...
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AD5412/AD5422 DATA REGISTER The DATA register is addressed by setting the address word of the input shift register to 0x01. The data to be written to the DATA register is entered in positions D15 to D4 for the AD5412 and ...
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Preliminary Technical Data STATUS REGISTER The STATUS register is a read only register. The STATUS register functionality is shown in Table 19 and Table 20. Table 19. Decoding the STATUS Register MSB D15 D14 D13 D12 D11 Table 20. STATUS ...
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AD5412/AD5422 FEATURES FAULT ALERT The AD5412/AD5422 is equipped with a FAULT pin, this is an open-drain output allowing several AD5412/AD5422 devices to be connected together to one pull-up resistor for global fault detection. The FAULT pin is forced active by ...
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Preliminary Technical Data supply for other devices in the system termination for pull-up resistors. This facility offers the advantage of not having to bring a digital supply across an isolation barrier. The internal power supply is enabled ...
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AD5412/AD5422 Table 24. Programmable Slew Time values in seconds for a full-scale change on any output range 0.25 0.13 257732 198413 0.33 0.17 152439 0.43 0.21 0.50 0.25 131579 0.57 0.28 115741 69444 0.9 0.47 37594 1.7 0.87 ...
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Preliminary Technical Data APPLICATIONS INFORMATION DRIVING INDUCTIVE LOADS When driving inductive or poorly defined loads connect a 0.01µF capacitor between I and GND. This will ensure OUT stability with loads beyond 50mH. There is no maximum capacitance limit. The capacitive ...
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AD5412/AD5422 For all interfaces, the DAC output update is initiated on the rising edge of LATCH. The contents of the registers can be read using the readback function. LAYOUT GUIDELINES In any circuit where accuracy is important, careful consideration of ...
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Preliminary Technical Data THERMAL AND SUPPLY CONSIDERATIONS The AD5412/AD5422 is designed to operate at a maximum junction temperature of 125° important that the device is not operated under conditions that will cause the junction temperature to exceed this ...
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AD5412/AD5422 OUTLINE DIMENSIONS 7.90 7.80 7. TOP VIEW 1.20 MAX 0.15 0.65 SEATING 0.05 BSC PLANE 0.10 COPLANARITY Figure 69. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP] 6.00 BSC SQ PIN 1 INDICATOR TOP VIEW 12° ...
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... Preliminary Technical Data ORDERING GUIDE Model Resolution AD5412AREZ 12 Bits AD5412BREZ 12 Bits AD5412ACPZ 12 Bits AD5412BCPZ 12 Bits AD5422AREZ 16 Bits AD5422BREZ 16 Bits AD5422ACPZ 16 Bits AD5422BCPZ 16 Bits Temperature Range Package Description -40°C to 85°C 24 Lead TSSOP_EP -40°C to 85°C 24 Lead TSSOP_EP -40°C to 85°C 40 Lead LFCSP -40° ...
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AD5412/AD5422 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06996-0-4/08(PrF) Preliminary Technical Data Rev. PrF | Page ...