AD5263 AD [Analog Devices], AD5263 Datasheet - Page 3

• Manufacturer Part Number: AD5263
• Description: Preliminary Technical Data
• Manufacturer: AD [Analog Devices]

Quad +15V Digital Potentiometers
ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION
V
Parameter
SPI (DIS=’0’) INTERFACE TIMING CHARACTERISTICS applies to all parts (Notes 6,12)
Input Clock Pulse Width
Data Setup Time
Data Hold Time
CLK to SDO Propagation Delay
CS Setup Time
CS High Pulse Width
Reset Pulse Width
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
I
SCL Clock Frequency
t
t
t
t
t
t
t
t
t
t
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
08 AUG ’02, REV PrD
2
BUF
HD;STA
LOW
HIGH
SU;STA
HD;DAT
SU;DAT
F
R
SU;STO
C (DIS=’1’) INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12)
A
Fall Time of both SDA & SCL signals
Rise Time of both SDA & SCL signals
= +V
Bus free time between
Low Period of SCL Clock
High Period of SCL Clock
Typicals represent average readings at +25°C and V
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the
relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. I
V
INL and DNL are measured at V
DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions.
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
Worst case supply current consumed when input all logic-input levels set at 2.4V, standard characteristic of CMOS logic.
P DISS is calculated from (I DD x V DD ). CMOS logic level inputs result in minimum power dissipation.
All dynamic characteristics use V
Measured at a V W pin where an adjacent V W pin is making a full-scale voltage change.
See timing diagram for location of measured values. All input control voltages are specified with t R =t F =2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics
are measured using V
Propagation delay depends on value of V
The AD5260/AD5262 contains 1,968 transistors. Die Size: 89mil x 105mil, 9,345sq. mil.
AB
Setup Time For START Condition t
Hold Time (repeated START)
Data Hold Time
Data Setup Time
Setup time for STOP Condition
DD
= V
, V
DD
, Wiper (V
B
= 0V, -40°C < T
W
) = No connect
L
= +5V.
STOP & START
W
DD
13
with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = V
A
= +5V, V
PRELIMINARY TECHNICAL DATA
< +125°C unless otherwise noted.)
DD
, R
SS
L
, and C
Symbol
= -5V, V
t
t
t
t
t
t
t
t
t
CH
DS
DH
PD
CSS
CSW
RS
CSH
CS1
f
t
t
t
t
t
t
t
t
t
SCL
1
2
3
4
5
6
7
8
9
10
,t
DD
CL
L
= +5V, V
see applications text.
L
=
+5V.
SS
Conditions
Clock level high or low
R
After this period the first clock pulse is generated
= -5V.
L
= 1K , C
L
< 20pF
- 3 -
W
= V
DD
/R for both V
DD
=+5V, V
SS
=-5V.
Min
100
1.3
0.6
1.3
0.6
0.6
0.6
50
20
20
20
40
90
10
1
0
0
0
DD
and V
(V
B
DD
= 0V.
Typ
= +5V, V
1
SS
Max
150
400
300
300
0.9
= -5V, V
AD5263
L
= +5V,
Units
KHz
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns