TBS6416B4E-7G ETC2 [List of Unclassifed Manufacturers], TBS6416B4E-7G Datasheet - Page 3

• Manufacturer Part Number: TBS6416B4E-7G
• Description: 1M x 16Bit x 4 Banks synchronous DRAM
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

M
PIN FUNCTION DESCRIPTION
Revision_1.1
A0~ A11
BS0, BS1
DQ0 ~DQ15
/CS
/RAS
/CAS
/WE
UDQM/LDQM
CLK
CKE
Vcc
Vss
Vcc
Vss
NC
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Pin Name
Address
Bank
Data Input / Output
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Input /output mask
Clock Input
Clock Enable
Power (+3.3 V)
Ground
Q Power (+ 3.3 V) for I/O
buffer
Q Ground for I/O buffer
No Connection
Function
Multiplexed pins for row and column address Row address: A0~ A11.
Column address: A0 ~ A7.
Select bank to activate during row address latch time, or bank to
read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command decoder is
disabled, new command is ignored and previous operation continues.
Command input. When sampled at the rising edge of the clock, /RAS,
/CAS and /WE define the operation to be executed.
Referred to /RAS
Referred to /RAS
The output buffer is placed at Hi-Z (with latency of 2) when DQM is
sampled high in read cycle. In write cycle, sampling DQM high will
block the write operation with zero latency.
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE is low,
Power Down mode, Suspend mode, or Self Refresh mode is entered.
Power for input buffers and logic circuit inside DRAM.
Ground for input buffers and logic circuit inside DRAM.
Separated power from
Separated ground from
No connection
3
TwinMOS Technologies Inc.
VCC
VSS
, used for output buffers to improve noise.
, used for output buffers to improve noise.
Description
TBS6416B4E
Sep. 2000