LT4256 LINER [Linear Technology], LT4256 Datasheet - Page 12

• Manufacturer Part Number: LT4256
• Description: UV, OV and Reverse Supply Protection Controller Low Operating Current: 125?A
• Manufacturer: LINER [Linear Technology]

LTC4365
APPLICATIONS INFORMATION
Gentle Shutdown
The SHDN input turns off the external MOSFETs in a
gentle, controlled manner. When SHDN is asserted low,
a 90μA current sink slowly begins to turn off the external
MOSFETs.
Once the voltage at the GATE pin falls below the voltage
at the V
feedback loop takes over. This loop forces the GATE voltage
The trace at V
to the negative voltage at V
reverse supply protection. The waveforms of Figure 7 were
captured using a 40V dual N-channel MOSFET, a 10μF
ceramic output capacitor and no load current on V
Recovery Timer
The LTC4365 has a recovery delay timer that filters noise
at V
or UV fault has occurred, the input supply must return to
the desired operating voltage window for at least 36ms in
order to turn the external MOSFET back on as illustrated
in Figures 4 and 5.
Going out of and then back into fault in less than 36ms
will keep the MOSFET off continuously. Similarly, coming
out of shutdown (SHDN low to high) triggers an 800μs
start-up delay timer (see Figure 10).
The recovery timer is also active while the LTC4365 is
powering up. The 36ms timer starts once V
V
power good window. See Figure 8.
12
IN(UVLO)
GATE
V
IN
IN
and helps prevent chatter at V
Figure 8. Recovery Timing During Power-On
(OV = GND, UV = SHDN = V
OUT
and V
pin, the current sink is throttled back and a
OUT
IN
, on the other hand, does not respond
lies within the user selectable UV/OV
MOSFET OFF
V
IN(UVLO)
IN
, demonstrating the desired
t
RECOVERY
IN
)
OUT
. After either an OV
IN
rises above
MOSFET ON
4365 F08
OUT
.
to track V
V
is pulled to within 400mV of ground.
Gentle gate turn off reduces load current slew rates and
mitigates voltage spikes due to parasitic inductances.
To further decrease GATE pin slew rate, place a capaci-
tor across the gate and source terminals of the external
MOSFETs. The waveforms of Figure 9 were captured using
the Si4230 dual N-channel MOSFETs, and a 2A load with
100μF output capacitor.
FAULT Status
The FAULT high voltage open drain output is driven low if
SHDN is asserted low, if V
voltage window, or if V
Figures 4, 5 and 10 show the FAULT output timing.
OUT
FAULT
SHDN
GATE
V
OUT
decays. Note that when V
5V/DIV
GND
Figure 9. Gentle Shutdown: GATE Tracks V
V
OUT
OUT
ΔV
Figure 10. Gentle Shutdown Timing
GATE
SHDN
V
Decays
GATE
OUT
, thus keeping the external MOSFETs off as
t
GATE(SLOW)
t
SHDN(F)
IN
100μs/DIV
IN
has not risen above V
is outside the desired UV/OV
GATE = V
OUT
OUT
< 4.5V, the GATE pin
t
START
V
T = 25°C
IN
= 12V
4365 F9
OUT
as
IN(UVLO)
4365 F10
4365f
.