T81L0010B-AL TMT [Taiwan Memory Technology], T81L0010B-AL Datasheet
T81L0010B-AL
Related parts for T81L0010B-AL
T81L0010B-AL Summary of contents
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... CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. 3. Order Information Part number Oscillator type T81L0010B-AL RC T81L0010B-BL Crystal P. 1 Publication Date: JAN. 2006 Package 32-pin LQFP ...
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... TM Technology Inc. reserves the right to change products or specifications without notice. RAM Stack Pointer TMP2 TMP1 ALU PSW Port 3 Latch Port 3 Port 1 Drivers Drivers P3.0 -P3.5, P3.7 P1.0 -P1 Preliminary T81L0010B OTP EEPROM ROM EEPROM interface Program Address Register Buffer PC Incrementer Program Counter DPTR Port 1 Latch Publication Date: JAN ...
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... ( LQFP-32 For RC Oscillator T81L0010B- ( ...
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... General-purpose I/O pin I/O General-purpose I/O pin I/O 3.3V power supply. Reset signal input or programming supply voltage input. I I/O General-purpose I/O pin (Default) or Serial input port. I/O General-purpose I/O pin (Default) or Serial output port. RC oscillator external resister connect pin connect P. 4 Preliminary T81L0010B Description Publication Date: JAN. 2006 Revision:A ...
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... =-45uA =-70uA =12mA V =MIN =25mA =40mA IL OL Conditions Min V =3. =3. Preliminary T81L0010B Units °C °C Min Typ Max Units 3.0 3 0 0.6 2 2.4 1.9 0 0.4 0.6 Typ Max Units 12 24 MHz 12 - MHz 10 - system cycle ...
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... Bank 1 (08H–0fH) (1,0)— Bank 2 (10H–17H) (1,1)— Bank 3 (18H–17H) TM Technology Inc. reserves the right to change products or specifications without notice. TL2 TH2 TL0 TL1 TH0 TH1 DPL DPH F0 RS1 RS0 P. 6 Preliminary T81L0010B PCON OV -- Publication Date: JAN. 2006 P Revision:A ...
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... Reception is initiated in Mode 0 by the condition RI = ‘0’ and REN = ‘1’. Reception is initiated in the other modes by the incoming start bit if REN = ‘1’. TM Technology Inc. reserves the right to change products or specifications without notice. Preliminary T81L0010B P. 7 Publication Date: JAN. 2006 Revision:A ...
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... Mode 2 Baud Rate =2 /64* (Oscillator Frequency) In the T81L0010B, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate. Using Timer 1 to Generate Baud Rates When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow ...
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... DATAR_L EEPROM read low byte Bit 4 Bit 3 Bit 2 Reserved Bit 4 Bit 3 Bit 2 Port3.4 Port3.3 Port3.2 Bit 4 Bit 3 Bit 2 Port1.4 Port1.3 Port1 Preliminary T81L0010B Comments LSB Bit1 Bit 0 LSB Bit1 Bit 0 Port3.1 Port3.0 LSB Bit1 Bit 0 Port1.1 Port1.0 Publication Date: JAN. 2006 Revision:A ...
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... TE CH 9.3. EEPROM Interface The EEPROM interface timing is fully compatible with 93C46. To access or send data from/to T81L0010B , 6 registers are going to be controlled. EEPROM Register Control Default -- SPICON 00H -- OPCODE 00H DATAW_H 00H DATAW_L DATAR_H 00H DATAW_L SPICON: MSB Bit 7 Bit 6 Bit5 Epst: start EEPROM timing. “1” to start and will be auto cleared after timing finish. ...
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... P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) P3.7 General purpose I/O only TM Technology Inc. reserves the right to change products or specifications without notice. Preliminary T81L0010B P. 11 Publication Date: JAN. 2006 Revision:A ...
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... TM Technology Inc. reserves the right to change products or specifications without notice trel P. 12 Preliminary T81L0010B Publication Date: JAN. 2006 Revision:A ...
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... The wdtrel register can be loaded and read any time TM Technology Inc. reserves the right to change products or specifications without notice. es0 et1 ps pt1 Preliminary T81L0010B LSB ex1 et0 ex0 LSB px1 pt0 px0 LSB Publication Date: JAN. 2006 ...
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... Tclk: clock period wdt: watchdog timer registers wdts: watchdog timer status flag reset: external reset input rst: internally generated reset signal TM Technology Inc. reserves the right to change products or specifications without notice. Preliminary T81L0010B rst_ff rst P. 14 Publication Date: JAN. 2006 Revision:A ...
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... LLD 0-A 7 from 8-A 15 from D PH Ext ernal ory R ead C ycl Preliminary T81L0010B IN STR 8-A 15 Publication Date: JAN. 2006 Revision:A ...
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... 8 Ext er nal ory ycl e S1.........S6 S1.........S6 S1......... Serial Port Mode Preliminary T81L0010B S1.........S6 S1.........S6 S1.........S6 S1......... Publication Date: JAN ...
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... TM Technology Inc. reserves the right to change products or specifications without notice Serial Port Mode Serial Port Mode Preliminary T81L0010B Publication Date: JAN. 2006 Stop Bit Stop Bit Stop Bit ...
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... TE CH PACKAGE DIMENSIONS ! LQFP-32 Package TM Technology Inc. reserves the right to change products or specifications without notice. Preliminary T81L0010B P. 18 Publication Date: JAN. 2006 Revision:A ...
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... Technology Inc. reserves the right to change products or specifications without notice. Preliminary T81L0010B P. 19 Publication Date: JAN. 2006 Revision:A ...