LP3933SL NSC [National Semiconductor], LP3933SL Datasheet - Page 7

• Manufacturer Part Number: LP3933SL
• Description: Lighting Management System for Six White LEDs and Two RGB or FLASH LEDs
• Manufacturer: NSC [National Semiconductor]

LOGIC INPUTS SS, SI, SCK, PWM_LED
V
V
I
f
LOGIC INPUT NRST
V
V
I
t
LOGIC OUTPUT SO
V
V
I
I
SCK
I
NRST
L
IL
IH
IL
IH
OL
OH
Logic Interface Characteristics
(1.8V ≤ V
SPI Interface
LP3933 is compatible with the SPI serial bus specification
and it operates as a slave. The transmission consists of
16-bit Write and Read Cycles. One cycle consists of 7 Ad-
dress bits, 1 Read/Write (R/W) bit and 8 Data bits. R/W bit
high state defines a Write Cycle and low defines a Read
Cycle. SO output is normally in high-impedance state and it
is active only when Data is sent out during a Read Cycle. A
pull-up or pull-down resistor may be needed in SO line, if a
Symbol
DD_IO
Input Low Level
Input High Level
Logic Input Current
Clock Frequency
Input Low Level
Input High Level
Logic Input Current
Reset Pulse Width
Output Low Level
Output High Level
Output Leakage Current V
≤ V
DD1,2
Parameter
)
V
I
I
SO
SO
DD_IO
SO
= 3 mA
= − 3 mA
= 2.8V
Conditions
= 2.775V
SPI Write Cycle
SPI Read Cycle
7
floating logic signal can cause unintended current consump-
tion in the input where SO is connected. The Address and
Data are transmitted MSB first. The Slave Select signal SS
must be low during the Cycle transmission. SS resets the
interface when high and it has to be taken high between
successive Cycles. Data is clocked in on the rising edge of
the SCK clock signal, while data is clocked out on the falling
edge of SCK.
V
V
DD_IO
DD_IO
−1.0
−1.0
Min
1.5
10
− 0.5
− 0.5
V
DD_IO
Typ
0.3
− 0.3
Max
0.5
1.0
0.5
1.0
0.5
1.0
13
20080512
20080511
www.national.com
Units
MHz
µA
µA
µA
µs
V
V
V
V
V
V