SM8578BV Nippon_Precision_Circuits America, SM8578BV Datasheet - Page 7

• Manufacturer Part Number: SM8578BV
• Description: Real-time Clock ic
• Manufacturer: Nippon_Precision_Circuits America

and bits 6 and 7 in the year register) are set to 1 (for
example, Year: 0010 1001
value that results can then be used to indicate over-
flow, serving the same function as an fr flag. The cor-
rect value of the register is restored when CE goes
LOW.
Alarm registers (address 7 to A)
An alarm can be set for day, weekday, hour and
minute. The weekday alarm register settings corre-
spond to the weekdays as shown in the following
table. The alarm setting can also be set for more than
one weekday by setting more than one bit to 1. Note
that if a weekday alarm is set, then the hour alarm,
minute alarm or both should be set; the alarm may
not be output correctly if only a weekday alarm is
set.
Bit 7 of each of the alarm registers is an alarm enable
bit (AE). When AE is 0, the register contents are
compared with the corresponding clock timer regis-
ter contents to determine when the alarm condition
has occurred. When AE is 1, all data bits in the regis-
ter are considered as don’t care bits. In this case, the
data is ignored and the alarm condition is always
active for all valid values of that register. Thus AE
can be used to set regular alarms, such as hourly or
daily alarms regardless of the current hour or day.
When the alarm interrupt enable bit (AIE) in register
address E is 0, alarm output on INTN is disabled.
TIE and FE must be set to 0, and AIE set to 1 to
enable the alarm interrupt function.
Timer registers (address C to E)
The timer registers control an 8-bit presettable down-
counter. The timer counter in register address D
counts down using the source clock frequency
assigned by bits TD0 and TD1 in register address C,
as shown in the following table. When the counter
becomes zero, generating a timer interrupt event,
INTN goes LOW. The counter is then reloaded with
the preset count and count down starts again. Thus
the timer counter is used as an interval timer.
A d dress 9
Bit 0 = 1
Bit 1 = 1
Bit 2 = 1
Bit 3 = 1
Bit 4 = 1
Bit 5 = 1
Bit 6 = 1
1110 1001). The illegal
Wednesday
W e e k d ay
Thursday
Saturday
Tuesday
Monday
Sunday
Friday
SM8578BV
When the timer interrupt enable bit (TIE) in register
address E is 0, timer output on INTN is disabled.
AIE and FE must be set to 0, and TIE set to 1 to
enable the timer interrupt function. TI/TP controls
the timer output mode.
The presettable down-counter is loaded with new
data whenever a write to register address D occurs.
Note that when the timer interrupt is disabled (TIE =
0), the data in register address D is stored and thus
register address D can be used as general-purpose
RAM, just as described for the don’t care bits in the
register table.
When the timer enable bit (TE) is 0, the timer
counter data is loaded into the counter. The count is
then started by setting TE to 1.
Output frequency register (address B)
The output frequency on INTN is determined by the
frequency divider ratio set by FD0 to FD2 and by the
source clock frequency set by FD3 and FD4, as
shown in the following tables. AIE and TIE should
be 0 when setting the output frequency. When the
frequency output enable bit (FE) is 0, INTN is in a
high-impedance state.
F D 2
0
0
0
0
1
1
1
1
T D 0
F D 4
0
0
1
1
0
0
1
1
F D 1
0
0
1
1
0
0
1
1
NIPPON PRECISION CIRCUITS—7
T D 1
F D 3
0
1
0
1
0
1
0
1
F D 0
0
1
0
1
0
1
0
1
1/60 Hz (1 min)
S o u rce clock
S o u rce clock
1 Hz (1 s)
32768 Hz
4096 Hz
1024 Hz
Divider ratio
64 Hz
32 Hz
1 Hz
1/10
1/15
1/30
1/1
1/2
1/3
1/6
1/5