sx1441 Semtech Corporation, sx1441 Datasheet - Page 54

• Manufacturer Part Number: sx1441
• Description: Bluetooth V1.2 Soc For Voice And Data Applications With Dsp Capabilities
• Manufacturer: Semtech Corporation

write to RegUartFifoTx
Personal Area Network
3.12.7 Reception
On detection of the start bit, the UartRxBusy bit is set. On detection of the stop bit, the received data and flags are
transferred from the internal shift register to the receive FIFO. At the same time, the bit UartRxDataReady and the
interrupts RxDataReady or RxComp are updated. The bit UartRxDataReady is set as long as the data present in
the FIFO are not read by the software. The interrupt RxDataReady is generated each time new data are written to
the FIFO. The interrupt RxComp is generated when only two free data words are left in the reception FIFO.
The flags in the register RegUartFifoRxSta give the status of the next word to be read in the reception FIFO.
Therefore, in order to know the status of the received data, RegUartFifoRxSta has to be read before reading the
actual data in RegUartFifoRx. Each data word in the reception FIFO has three flags associated to it: UartRxSErr,
UartRxPErr and UartRxFErr.
The bit UartRxSErr is set if a start error has been detected. The bit UartRxPErr is set if a parity error has been
detected, i.e. the received parity bit is not equal to the calculated parity of the received data. The bit UartRxFErr
shows that a frame error has been detected: no stop bit has been detected.
The UartRxFifoFull bit is set when the receive FIFO is full. If the FIFO is full and new data are transferred from the
shift register to FIFO, the bit UartRxFifoOErr (overflow error) is set and the new data are lost. Reading
RegUartFifoRxSta clears UartRxFifoOErr.
Writing any data to RegUartFifoRxSta resets the reception block: all flags in RegUartFifoRxSta are reset and data
in the reception FIFO that were not yet read by the software are lost.
RTS is used for the flow control. While the reception FIFO reached the threshold level, RTS is set. RTS is cleared
as soon as the software reads data in the reception FIFO depending on RtsLevelMode.
Figure 26 shows the timing diagram for a possible reception. In this example, the depth of the FIFO is 4. RTS1
shows the functionality when RtsLevelMode = 0 and RTS2 when RtsLevelMode = 1. The actual depth of the FIFO
is 8.
© Semtech 2006
write to RegUartFifoTx
UartTxFifoEmpty
UartTxFifoEmpty
UartTxBusy
shift enable
IrqTxEmpty
UartTxFifoFull
TxFifo(1)
TxFifo(0)
UartTxBusy
shift enable
IrqTxEmpty
CTSn
TxFifo(1)
TxFifo(0)
Tx
CTSn
Tx
Figure 25 - Uart transmission timing diagram back to back with FIFO depth = 2
word1
word1
Figure 24 - Uart transmission timing diagram with FIFO depth = 2.
word2
word2
start
bit0
start
bit1
54
bit0
bit1
bit7
bit2
parity stop
bit3
bit4
start
SX1441 – Bluetooth® 1.2 SoC
bit5
bit0
bit6
bit1
bit7
www.semtech.com
parity stop
bit7
Data Sheet
parity
stop