CS4330 CIRRUS [Cirrus Logic], CS4330 Datasheet
CS4330
Available stocks
Related parts for CS4330
CS4330 Summary of contents
Page 1
... D/A conversion and output analog filtering pin package. These devices differ in the serial interface format used to input audio data. The CS4330, CS4331 and CS4333 are based on delta- sigma modulation, where the modulator output controls the reference voltage input to an ultra-linear analog low- pass filter ...
Page 2
... 0 250 - - 3.33 3.70 4.07 1. 100 - - IA IA 140 160 - - 0 PSRR - CS4330, CS4331, CS4333 CS4330/31/33-BS VA +3V VA +5V only Typ Max Min Typ Max to 70 - 0.003 - - .003 .008 -85 -80 -88 -86 -79 - -72 -66 - -32 - 0.5 0.5 to 21. 21. 0.1 0 0.05 0.05 26. ...
Page 3
... MCLK / LRCK = 384 MCLK / LRCK = 256 MCLK / LRCK = 256 t sclkl t sclkh t sclkw t slrd t slrs t sdlrs t sdh (Note 6) t sclkw t sclkr t sdlrs MCLK / LRCK = 256 or 512 t sdh MCLK / LRCK = 384 t sdh CS4330, CS4331, CS4333 Min Typ Max 1000 15 - 1000 21 ...
Page 4
... LRCK SCLK SDATA **INTERNAL SCLK * LRCK for CS4331 ** The SCLK pulses shown are internal to the CS4330/31/33. LRCK MCLK *INTERNAL SCLK SDATA * The SCLK pulses shown are internal to the CS4330/31/33 slrs t slrd t t sdlrs External Serial Mode Input Timing *LRCK t sclkr ...
Page 5
... Symbol (VA+ = 5.5V (VA+ = 5.0V (Note max. (AGND = 0V; all voltages with respect to ground.) Symbol VA IND stg (AGND = 0V; all voltages with respect to Symbol (3V mode) VA+ (5V mode) VA+ CS4330, CS4331, CS4333 Min Typ Max Units Min Max Units -0 ...
Page 6
... Audio 2 Data DEM/SCLK Processor 3 LRCK 4 External Clock MCLK AOUTL + CS4330 CS4331 CS4333 AOUTR + AGND 6 * Required for AC coupling only ** )(2400 )(Fs)(2) Figure 1. Recommended Connection Diagram CS4330, CS4331, CS4333 +3V/+ 2.4k Left Audio C 56k * ** * 2.4k Right Audio C 56k * ** * 1 Output Output DS136F1 ...
Page 7
... GENERAL DESCRIPTION The CS4330, CS4331, and CS4333 are complete stereo digital-to-analog systems including digital interpolation, 128 third-order delta-sigma digi- tal-to-analog conversion, digital de-emphasis and analog filtering, Figure 2. This architecture pro- vides a high tolerance to clock jitter. The primary purpose of using delta-sigma modu- ...
Page 8
... The Left/Right Clock (LRCK) defines the channel and delineation of data and the Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4330, CS4331 and CS4333 differ in the serial data for- mat as shown in Figures 4-7. The Master Clock (MCLK) is used to operate the digital interpola- tion filter and the delta-sigma modulator ...
Page 9
... Figure 3. De-Emphasis Curve (Fs = 44.1kHz) Initialization and Power-Down The Initialization and Power-Down sequence flow chart is shown in Figure 8. The CS4330/31/33 enter the Power-Down mode upon initial power- up. The interpolation filters and delta-sigma modulators are reset, and the internal voltage ref- erence, one-bit digital-to-analog converters and switched-capacitor low-pass filters are powered down ...
Page 10
... External SCLK Mode Right Justified, 18-Bit Data Data Valid on Rising Edge of SCLK SCLK must have at least 36 cycles per LRCK Figure 4. CS4330 Data Format Internal SCLK Mode 16-Bit Data Data Valid on Rising Edge of SCLK ...
Page 11
... External SCLK Mode Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK must have at least 32 cycles per LRCK Figure 7. CS4333 SCLK Data Format CS4330, CS4331, CS4333 Right Channel ...
Page 12
... USER: Remove Clocks Normal Operation De-emphasis USER: Apply SDATA Analog Output is Generated Figure 8. CS4330/31/33 Initialization and Power-Down Sequence 12 USER: Apply Power Power-Down Mode USER: Apply MCLK and LRCK 256/384/512 MCLK/LRCK Determination Power Supply Determination + Volt mode USER: set SCLK mode ...
Page 13
... Fs. Note that the response plots have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs. Figure 11. CS4330/31/33 Combined Digital and Analog Filter Transition Band Figure 12. CS4330/31/33 Combined Digital and Analog Filter Passband Ripple ...
Page 14
... Audio Precision Dual Domain System One. All plots are done in +5V mode kHz sampling rate, and are shown in Fig- ures 13-20. Figure 13 shows the CS4330/31/33 frequency re- sponse. The response is flat to 20 kHz as specified. Figure 14 shows THD+N versus signal ampli- tude for a 1 kHz 20-bit dithered input signal ...
Page 15
... Dur- ing the fade, the output from the CS4330/31/33 is measured and compared to the ideal level. No- tice the very close tracking of the output level to the ideal, even at low level inputs. This indicates very good low-level linearity, one of the key benefits of delta-sigma digital-to-analog conver- sion ...
Page 16
... Configuration Register The CS4330, CS4331, CS4333 support multiple 2’s-complement data/clock formats. The required format is governed by the contents of the Con- figuration Register. The 5-bit register determines which serial data format is acceptable, the fre- quency of the Internal Serial Clock, on which edge of SCLK audio data must be valid, and the number of bits to be loaded into the input buffer ...
Page 17
... DEM/SCLK valid to LRCK falling setup time LRCK falling to DEM/SCLK hold time SDATA setup time SDATA hold time DS136F1 Figure 21. Configuration Operation Figure 22. Configuration Timing Symbol t clrs t clrh t setup t hold Table 2. Configuration Timing Characteristics CS4330, CS4331, CS4333 Min Typ Max Units ...
Page 18
... Audio Engineering Society, March 1992. 4)"An 18-Bit Stereo D/A Converter With Inte- grated Digital and Analog Filters" by Nav S. Sooch, Jeffrey W. Scott. Paper presented at the 91st Convention of the Audio Engineering Soci- ety, November 1991. 5)CDB4330/31/33 Evaluation board Data Sheet; DS136DB2 MAR’96 18 CS4330, CS4331, CS4333 DS136F1 ...
Page 19
... SDATA. SDATA - Audio Serial Data Input, PIN 1. Two’s complement MSB-first serial data is input on this pin. The data is clocked into the CS4330, CS4331, and CS4333 via internal or external SCLK and the channel is determined by LRCK. DEM/SCLK - De-emphasis / External serial clock input , PIN 2. ...
Page 20
... Interchannel Gain Mismatch - The gain difference between left and right channels. Units in decibels. Gain Error - The deviation from the nominal full scale analog output for a full scale digital input. Gain Drift - The change in gain value with temperature. Units in ppm CS4330, CS4331, CS4333 DS136F1 ...
Page 21
... Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC 8-pin Plastic SOIC DIM 8-Pin A SOIC CS4330, CS4331, CS4333 MILLIMETERS INCHES MIN MAX MIN MAX 5.15 5.35 0.203 0.210 1.27 TYP 0.050 TYP 0 0.25 0 0.010 1.77 1.88 0.070 ...
Page 22
Notes • ...
Page 23
... Evaluation Board for CS4330 / CS4331 / CS4333 Features Demonstrates recommended layout and grounding arrangements CS8412 Receives AES/EBU, S/PDIF, & EIAJ-340 Compatible Digital Audio Digital and Analog Patch Areas Requires only a digital signal source and power supplies for a complete Digital-to-Analog-Converter system Digital ...
Page 24
... Notice that the the system diagram also includes the interconnections between the partitioned schematics. CS4330/31/33 Digital to Analog Converter A description of the CS4330/31/33 is included in the CS4330/31/33 data sheet. CS8412 Digital Audio Receiver The system receives and decodes the standard S/PDIF data format using a CS8412 Digital Audio Receiver, Figure 4 ...
Page 25
... MCLK on the evaluation board. MCLK becomes an output with LRCK, SCLK and SDATA inputs. This technique insures that the CS4330/31/33 receives a jitter free clock to maximize performance. This can be accom- plished by installing a crystal oscillator into U5, see Figure 4 (the socket for U5 is located within the footprint for the CS8412) and placing J22 in the 1 position and J23 in the 0 position ...
Page 26
... CS8412 and digital section (VA+) for Analog output filter op-amp input (configured for +5V) input (VD+3/+5V) for Voltage Level Converter input (VA+3/+5V) for CS4330/31/33 input ground connection from power supply input digital audio interface input via coax input digital audio interface input via optical ...
Page 27
JUMPER PURPOSE selects channel for CSLR/FCK CS8412 channel status information Clock Selects source of Select system clocks and data J22 Selects MCLK as Input J23 or Output M0 M1 CS8412 mode select M2 M3 SCLK Selects SCLK Mode Selects source ...
Page 28
... Fig 6 Fig 5 MCLK LRCK SCLK SDATA CS8412 Digital Audio Power Interface Down Fig 3 Fig 4 28 MCLK Voltage LRCK Level SCLK Converter SDATA Fig 3 Figure 1. System Block Diagram and Signal Flow CDB4330, CDB4331, CDB4333 AOUTL Analog CS4330/31/33 AOUTR Fig 2 DS136DB2 Filter Fig 2 ...
Page 29
... Figure 2. CS4330/31/33 and Connections ...
Page 30
Figure 3. Voltage Level Conversion and Power Down Circuitry 30 CDB4330, CDB4331, CDB4333 DS136DB2 ...
Page 31
NOTE: U2 and U5 cannot be installed simultaneously Figure 4. CS8412 Digital Audio Receiver Connections ...
Page 32
Optical Toshiba part TORX173 available through Insight Electronics 32 Figure 5. I/O Interface for Clocks and Data Figure 6. Digital Audio Input CDB4330, CDB4331, CDB4333 DS136DB2 ...
Page 33
DS136DB2 CDB4330, CDB4331, CDB4333 Figure 7. Power Supply 33 ...
Page 34
Figure 8. CDB4330/31/33 Component Side Silkscreen 34 CDB4330, CDB4331, CDB4333 DS136DB2 ...
Page 35
DS136DB2 Figure 9. CDB4330/31/33 Component Side (top) CDB4330, CDB4331, CDB4333 35 ...
Page 36
Figure 10. CDB4330/31/33 Solder Side (bottom) CDB4330, CDB4331, CDB4333 DS136DB2 ...
Page 37
Notes • ...
Page 38
Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to ...