CS42426_05 CIRRUS [Cirrus Logic], CS42426_05 Datasheet - Page 30

• Manufacturer Part Number: CS42426_05
• Description: 114 dB, 192 kHz 6-Ch Codec with PLL
• Manufacturer: CIRRUS [Cirrus Logic]

30
4.5.3
DAC_SCLK
ADC_SCLK
DAC_LRCK
ADC_LRCK
ADCIN1/2
ADCIN1/ADCIN2 Serial Data Format
The two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, support
only left-justified, 24-bit samples at 64Fs or 128Fs. This interface is not affected by any of the serial port
configuration register bit settings. These serial data lines are used when supporting One-Line Mode of
operation with external ADCs attached. If these signals are not being used, they should be tied together
and wired to GND via a pull-down resistor.
For proper operation, the CS42426 must be configured to select which SCLK/LRCK is being used to clock
the external ADCs. The EXT ADC SCLK bit in register
set accordingly. Set this bit to ‘1’ if the external ADCs are wired using the DAC_SP clocks. If the ADCs
are wired to use the ADC_SP clocks, set this bit to ‘0’.
Left-Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
MSB
-1 -2 -3 -4 -5
24
+5 +4
Left Cha nnel
Figure 16. ADCIN1/ADCIN2 Serial Audio Format
SCLK Rate(s)
64, 128 Fs
64 Fs
not supported
+3 +2 +1
LSB
Notes
Single-Speed Mode, Fs= 32, 44.1, 48 KHz
Double-Speed Mode, Fs= 64, 88.2, 96 KHz
Quad-Speed Mode, Fs= 176.4, 192 KHz
“Misc Control (address 05h)” on page 46
MSB
-1 -2 -3 -4
+5 +4
R ight C han nel
+3 +2 +1
LSB
CS42426
DS604F1
must be