CS4239-JQ CIRRUS [Cirrus Logic], CS4239-JQ Datasheet - Page 50

• Manufacturer Part Number: CS4239-JQ
• Manufacturer: CIRRUS [Cirrus Logic]

LD1IM
Independent ADC Fs (X12)
Default = xxxxxxxx
SRAD7-SRAD0 Sample Rate frequency select for
Independent DAC Fs (X13)
Default = xxxxxxxx
SRDA7-SRDA0 Sample Rate frequency select for
Reserved, backwards compatible (X14)
Default = xxxxxxxx
rbc
Reserved, backwards compatible (X15)
Default = xxxxxxxx
rbc
Left Wavetable Serial Port Mute (X16)
Default = exxxxxx
LWM
50
SRDA7 SRDA6 SRDA5 SRDA4 SRDA3 SRDA2 SRDA1 SRDA0
SRAD7 SRAD6 SRAD5 SRAD4 SRAD3 SRAD2 SRAD1 SRAD0
LWM
D7
D7
D7
D7
rbc
D7
rbc
D6
res
D6
D6
D6
rbc
D6
rbc
D5
rbc
D5
rbc
Left DAC1 Input Mixer Mute.
When set to 1, the output from the
Left DAC1 is muted to the Left input
mixer. See Figure 4.
the A/D converter. See Table 10.
D5
the D/A converter. See Table 10.
Reserved, backwards compatible.
Reserved, backwards compatible.
Left Wavetable Serial Port Mute.
When set, the Left Wavetable Serial
Input to DAC2 is muted. The default
state of this bit is the inverse of
WTEN in the Hardware Configura-
tion Data, Global Configuration byte.
D5
D5
rbc
D4
rbc
D4
rbc
D4
D4
D4
rbc
D3
rbc
D3
rbc
D3
D3
D3
rbc
D2
rbc
D2
rbc
D2
D2
D2
rbc
D1
rbc
D1
rbc
D1
D1
D1
rbc
D0
D0
rbc
D0
D0
D0
rbc
rbc
Right Wavetable Serial Port Mute (X17)
Default = exxxxxxx
RWM
3D and RAM Port Enable (X18)
Default = 0xeeeee0
DLEN
ZVEN
PSH
DSPD1
3DEN
AUX1R
RWM
PAE
D7
D7
D6
D6
res
res
CrystalClear Portable ISA Audio System
AUX1R
D5
rbc
D5
Right Wavetable Serial Port Mute.
When set, the Right Wavetable Se-
rial Input to DAC2 is muted. The
default state of this bit is the inverse
of WTEN in the Hardware Configura-
tion Data, Global Configuration byte.
the input to DAC1 to comes from the
ADCs. While DLEN is on, no other
data is sent to DAC1. This provides
a test path that is generally not used
in normal operation.
ZVPORT Enable. When set, the
ZVPORT pins are enabled and se-
lected as input to DAC2. While the
ZVPORT is enabled, no other input
to DAC2 is allowed (synthesizers or
DSP).
Playback Sample Hold. When set, the
last sample is held in DAC1 when
PEN is cleared. When clear, zero is
sent to DAC1 when PEC is cleared.
DSP port controls DAC1. When set,
the serial DSP port controls DAC1 in-
stead of the ISA playback FIFO.
sound is enabled on L/ROUT. This
bit is also controlled through C3.
AUX1 Remap. When set, writes to
I18/19 (DAC2 volume) also control
the AUX1 volume. When clear,
I18/19 control DAC2 volume and
I2/3 control AUX1 volume. This bit
provides some backwards compatibil-
Digital Loopback Enable. When set,
3D Sound Enable. When set, 3D
D4
rbc
3DEN
D4
TM
D3
rbc
DSPD1 PSH ZVEN
D3
D2
rbc
D2
D1
D1
rbc
CS4239
DS253PP2
DLEN
D0
D0
rbc