mx98713 Macronix International Co., mx98713 Datasheet - Page 24

• Manufacturer Part Number: mx98713
• Description: 100/10base Pci Mac Controller
• Manufacturer: Macronix International Co.

13
12
11:10 LOM
9
7
6
5
4
3
2
1
0
------------------------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------------------------
CSR6<21>
------------------------------------------------------------------------------------------------------------------------------------------------
0
0
0
0
1
------------------------------------------------------------------------------------------------------------------------------------------------
Table 5 -- Transmit Threshold
ST
FC
FD
PM
PR
SB
IF
PB
HO
SR
HP
Start/Stop Transmission Command, set to place transmission process in running state and
will try to transmit current descriptor in transmit list. When reset, transmit process is placed in
stop state.
Force Collision Mode, used in collision logic test in internal loopback mode, set to force
collision during next transmission attempt. This can result in excessive collision reported in
TDES0<8> if 16 or more collisions.
Loopback Operation Mode, see table 7.
Full-Duplex Mode, set for simultaneous transmit and receive operation, heartbeat check is
disabled, TDES0<7> should be ignored, and internal loopback is not allowed. His bit is in the
UII port. When not MII port, Auto-negotiation process decides full-duplex or half-duplex.
Pass All Multicast, set to accept all incoming frames with a multicast destination address are
received. Incoming frames with physical address are filtered according to the CSR6<0> bit.
Promiscuous Mode, any incoming valid frames are accepted.
Start/Stop Backoff Counter, when reset, the backoff timer is not affected by the network
carrier activity. Otherwise, timer will start counting when carrier drops.
Inverse Filtering, read-only bit, set to operate in inverse filtering mode; only valid during
perfect filtering mode.
Pass Bad Frames, set to pass bad frame mode, all incoming frames passing the address
filtering are accepted including runt frames, collided fragments, truncated frames caused by
FIFO overflow.
Hash-Only Filtering Mode, read-only bit, set to operate in imperfect filtering mode for both
physical and multicast addresses.
Start/Stop Receive, set to place receive process in running state where descriptor acquisition
is attempted from current position in the receive list. Reset to place the receive process in
stop state.
Hash/Perfect Receive Filtering Mode, read only bit, set to use hash table to filter multicast
incoming frames. If CSR6<2> is also set, then the physical addresses are imperfect address
filtered too. If CSR6<2> is reset, then physical addresses are perfect address filtered,
according to a single physical address as specified in setup frame.
CSR6<15:14>
00
01
10
11
XX
CSR6<22>=0
128
256
512
1024
( Store and Forward )
24
CSR6<22>=1 (Threshold bytes)
72
96
128
160
MX98713
INDEX