a10v20b Actel Corporation, a10v20b Datasheet - Page 8

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a10v20b

Manufacturer Part Number
a10v20b
Description
Act? 1 Series Fpgas
Manufacturer
Actel Corporation
Datasheet

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Equivalent Capacitance
The power dissipated by a CMOS circuit can be expressed by
the Equation 1.
Where:
Equivalent capacitance is calculated by measuring I
at a specified frequency and voltage for each circuit
component of interest. Measurements have been made over a
range of frequencies at a fixed value of V
capacitance is frequency independent so that the results may
be used over a wide range of operating conditions. Equivalent
capacitance values are shown below.
C
To calculate the active power dissipated from the complete
design, the switching frequency of each part of the logic must
be known. Equation 2 shows a piece-wise linear summation
over all components.
Power = V
(n * C
0.5 * (q
(r
Where:
1-290
Modules (C
Input Buffers (
Output Buffers (C
Routed Array Clock Buffer
Loads (C
m
n
p
q
r
1
EQ
1
1
* f
C
V
F is the switching frequency in MHz.
Values for Actel FPGAs
q1
CC
EQ
EQI
1
)
routed_Clk1
is the power supply in volts.
* C
is the equivalent capacitance expressed in pF.
* f
EQCR
= Number of logic modules switching at fm
= Number of input buffers switching at fn
= Number of output buffers switching at fp
= Number of clock loads on the first routed array
= Fixed capacitance due to first routed array
CC
n
EQCR
EQM
)
2
clock (All families)
clock (All families)
inputs
* [(m * C
Power (uW) = C
)
CEQI
)
* f
EQO
]
+ (p * (C
q1
)
)
)
routed_Clk1
EQM
* f
EQO
m
EQ
)
+ C
modules
+
* V
L
A10V10B
A10V20B
) * f
CC2
10.9
11.6
+
3.2
4.1
* F
p
)
outputs
CC
. Equivalent
+
A1010B
A1020B
22.1
31.2
CC
4.6
3.7
active
(1)
(2)
Fixed Capacitance Values for Actel FPGAs
(pF)
Determining Average Switching Frequency
To determine the switching frequency for a design, you must
have a detailed understanding of the data input values to the
circuit. The following guidelines are meant to represent
worst-case scenarios so that they can be generally used to
predict the upper limits of power dissipation. These
guidelines are as follows:
C
C
C
C
C
f
f
f
f
Logic Modules (m)
Inputs switching (n)
Outputs switching (p)
First routed array clock loads (q
Load capacitance (C
Average logic module switching rate (f
Average input switching rate (f
Average output switching rate (f
Average first routed array clock rate
(f
m
n
p
q1
EQM
EQI
EQO
EQCR
L
q1
)
Device Type
A1010B
A1020B
A10V10B
A10V20B
= Equivalent capacitance of logic modules in pF
= Equivalent capacitance of input buffers in pF
= Equivalent capacitance of output buffers in pF
= Equivalent capacitance of routed array clock in
= Output lead capacitance in pF
= Average logic module switching rate in MHz
= Average input buffer switching rate in MHz
= Average output buffer switching rate in MHz
= Average first routed array clock rate in MHz (All
pF
families)
L
)
n
routed_Clk1
)
1
p
)
)
41.4
68.6
40
65
r
1
m
) F/10
90% of modules
#inputs/4
#outputs/4
40% of modules
35 pF
F/5
F/10
F

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