A1280DX-1CQB ACTEL [Actel Corporation], A1280DX-1CQB Datasheet - Page 34
![no-image](/images/no-image-200.jpg)
A1280DX-1CQB
Manufacturer Part Number
A1280DX-1CQB
Description
Integrator Series FPGAs: 1200XL and 3200DX Families
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.A1280DX-1CQB.pdf
(84 pages)
- Current page: 34 of 84
- Download datasheet (5Mb)
A 3 2 65 D X T i m i n g C h a ra c t er i s ti c s
(Worst-Case Commercial Conditions V
Notes:
1.
2.
3.
4.
5.
34
Parameter
Logic ModulePropagation Delays
Combinatorial Functions
t
t
Predicted Routing Delays
t
t
t
t
t
t
Sequential Timing Characteristics
t
t
t
t
t
t
t
t
t
PD
PDD
RD1
RD2
RD3
RD4
RD5
RDD
CO
GO
SUD
HD
RO
SUENA
HENA
WCLKA
WASYN
For dual-module macros, use t
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
performance. Post-route timing analysis or simulation is required to determine actual performance.
Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained from
the DirectTime Analyzer utility.
Set-up and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External set-up/hold timing
parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input subtracts
(adds) to the internal set-up (hold) time.
V
CC
= 3.0V for 3.3V specifications.
Description
Internal Array Module Delay
Internal Decode Module Delay
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
Flip-Flop Clock-to-Output
Latch Gate-to-Output
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset to Output
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active Pulse Width
Flip-Flop (Latch) Asynchronous Pulse Width
2
1
3, 4
PD1
+ t
RD1
+ t
PDn
, t
CO
+ t
CC
Min.
0.35
0.75
0.0
0.0
3.7
4.9
‘–3’ Speed
RD1
Discontinued – v3.0
= 4.75 V, T
I n t e g r a to r S e r i e s F P G A s : 1 2 0 0 X L a n d 3 2 0 0 D X F a m i l i e s
+ t
Max.
0.46
PDn
2.1
2.5
0.3
0.7
1.0
1.4
2.7
2.3
2.1
2.3
or t
PD1
Min.
0.4
0.0
0.9
0.0
4.2
5.5
‘–2’ Speed
+ t
J
RD1
= 70°C)
Max.
2.4
2.8
0.4
0.8
1.2
1.6
3.2
0.5
2.7
2.4
2.7
+ t
SUD
Min.
0.47
, whichever is appropriate.
0.0
1.0
0.0
4.9
6.5
‘–1’ Speed
Max.
0.62
2.9
3.4
0.5
0.9
1.4
1.9
3.7
3.1
2.9
3.1
Min.
‘Std’ Speed
0.6
0.0
1.3
0.0
6.4
8.4
Max.
3.7
4.4
0.6
1.2
1.8
2.4
4.9
0.8
4.1
3.7
4.1
Min.
0.5
0.0
1.1
0.0
5.5
7.1
‘–F’ Speed
Max.
3.2
3.7
0.5
1.0
1.6
2.1
4.1
0.7
3.5
3.2
3.5
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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