DS1922T-F5 MAXIM [Maxim Integrated Products], DS1922T-F5 Datasheet - Page 42

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DS1922T-F5

Manufacturer Part Number
DS1922T-F5
Description
Temperature Logger iButton With 8kB Datalog Memory
Manufacturer
MAXIM [Maxim Integrated Products]
Datasheet
The sum of t
define the master sampling window (t
For most reliable communication, t
later than t
sufficient recovery time t
IMPROVED NETWORK BEHAVIOR
In a 1-Wire environment line termination is possible only during transients controlled by the bus master (1-Wire
driver). 1-Wire networks, therefore are susceptible to noise of various origins. Depending on the physical size and
topology of the network, reflections from end points, and branch points can add up or cancel each other to some
extent. Such reflections are visible as glitches or ringing on the 1-Wire communication line. Noise coupled onto the
1-Wire line from external sources can also result in signal glitching. A glitch during the rising edge of a time slot can
cause a slave device to lose synchronization with the master and, as a consequence, result in a search ROM
command coming to a dead end or cause a device-specific function command to abort. For better performance in
network applications, the DS1922L/T uses a new 1-Wire front end, which makes it less sensitive to noise and also
reduces the magnitude of noise injected by the slave device itself.
The 1-Wire front end of the DS1922L/T differs from traditional slave devices in four characteristics:
1) The falling edge of the presence pulse has a controlled slew rate. This provides a better match to the line
2) There is additional low-pass filtering in the circuit that detects the falling edge at the beginning of a time slot.
3) There is a hysteresis at the low-to-high switching threshold V
4) There is a time window specified by the rising edge hold-off time t
Only devices which have the parameters t
improved 1-Wire front end.
Figure 14. Noise Suppression Scheme
CRC GENERATION
With the DS1922L/T there are two different types of CRCs (Cyclic Redundancy Checks). One CRC is an 8-bit type
and is stored in the most significant byte of the 64-bit ROM. The bus master can compute a CRC value from the
first 56 bits of the 64-bit ROM and compare it to the value stored within the DS1922L/T to determine if the ROM
data has been received error-free. The equivalent polynomial function of this CRC is: X
CRC is received in the true (non-inverted) form. It is computed at the factory and lasered into the ROM.
The other CRC is a 16-bit type, generated according to the standardized CRC16-polynomial function x
+ 1. This CRC is used for error detection when reading register pages or the datalog memory using the Read
Memory with CRC command and for fast verification of a data transfer when writing to or reading from the
scratchpad. In contrast to the 8-bit CRC, the 16-bit CRC is always communicated in the inverted form. A CRC-
generator inside the DS1922L/T (Figure 15) calculates a new 16-bit CRC as shown in the command flow chart of
Figure 9. The bus master compares the CRC value read from the device to the one it calculates from the data and
V
impedance than a digitally switched transistor, converting the high frequency ringing known from traditional
devices into a smoother low-bandwidth transition. The slew rate control is specified by the parameter t
which has different values for standard and Overdrive speed.
This reduces the sensitivity to high-frequency noise. This additional filtering does not apply at Overdrive speed.
below V
even if they extend below V
that appear late after crossing the V
will be taken as beginning of a new time slot (Figure 14, Case C, t
HY
V
V
PUP
0V
TH
MSRMAX
TH
RL
- V
+ δ (rise rime) on one side and the internal timing generator of the DS1922L/T on the other side
HY
. After reading from the data line, the master must wait until t
, it will not be recognized (Figure 14, Case A). The hysteresis is effective at any 1-Wire speed.
Case A
REC
for the DS1922L/T to get ready for the next time slot.
TH
RL
- V
should be as short as permissible and the master should read close to but no
MSRMIN
HY
TH
threshold (Figure 14, Case B, t
threshold and extend beyond the t
to t
FPD
MSRMAX
, V
t
Case B
GL
t
HY
REH
42 of 50
) in which the master must perform a read from the data line.
and t
REH
specified in their electrical characteristics use the
TH
. If a negative glitch crosses V
GL
GL
≥ t
REH
REH
< t
during which glitches will be ignored,
REH
REH
).
t
REH
t
Case C
GL
). Deep voltage droops or glitches
window cannot be filtered out and
SLOT
is expired. This guarantees
8
+ X
5
DS1922L/DS1922T
+ X
TH
4
but doesn’t go
+ 1. This 8-bit
16
+ x
15
+ x
FPD
2
,

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