ex256-ptq64pp Actel Corporation, ex256-ptq64pp Datasheet - Page 22

• Manufacturer Part Number: ex256-ptq64pp
• Description: Ex Family Fpgas
• Manufacturer: Actel Corporation

eX Timing Model
Note: Values shown for eX128–P, worst-case commercial conditions (5.0V, 35pF Pad Load).
Figure 1-14 • eX Timing Model
Hardwired Clock
External Setup =
Clock-to-Out (Pad-to-Pad), typical
1 -1 8
eX Family FPGAs
Hard-Wired
Routed
Clock
Clock
=
=
=
I/O Module
I/O Module
t
0.7 + 0.3 + 0.5 – 1.1 = 0.4 ns
t
1.1 + 0.6 + 0.3 + 2.6 = 4.6 ns
t
t
Input Delays
INYH
HCKH
INYH
INYH
t
HCKH
t
RCKH
(100% Load)
= 0.7 ns
= 1.3 ns
+ t
+ t
= 1.1 ns
IRD1
= 1.3 ns
RCO
+ t
+ t
SUD
RD1
t
t
t
t
t
IRD1
IRD2
IRD1
t
t
SUD
HD
SUD
HD
– t
+ t
= 0.0 ns
= 0.0 ns
HCKH
= 0.3 ns
= 0.4 ns
= 0.3 ns
= 0.5 ns
DHL
= 0.5 ns
t
t
Register
Register
RCO
RCO
D
D
Cell
Cell
Internal Delays
Combinatorial
t
= 0.6 ns
= 0.6 ns
v4.3
PD
Cell
Q
Q
= 0.7 ns
Routed Clock
External Setup =
Clock-to-Out (Pad-to-Pad), typical
t
t
RD1
RD1
= 0.3 ns
= 0.3 ns
t
t
t
RD1
RD4
RD8
Predicted
Routing
Delays
= 0.3 ns
= 0.7 ns
= 1.2 ns
=
=
=
t
0.7 + 0.4 + 0.5 – 1.3= 0.3 ns
t
1.3+ 0.6 + 0.3 + 2.6 = 4.8 ns
I/O Module
I/O Module
INYH
RCKH
t
t
DHL
DHL
I/O Module
= 2.6 ns
= 2.6 ns
t
t
+ t
ENZL
+ t
ENZL
Output Delays
IRD2
RCO
= 1.9 ns
= 1.9 ns
t
DHL
+ t
+ t
SUD
RD1
= 2.6 ns
– t
+ t
RCKH
DHL