oxfw911 ETC-unknow, oxfw911 Datasheet - Page 10

• Manufacturer Part Number: oxfw911
• Description: Ieee1394 To Ata/atapi Native Bridge
• Manufacturer: ETC-unknow

Data Sheet Rev 1.1
OXFORD SEMICONDUCTOR LTD.
Symbol
tiordyz
tziordy
t2cyc
t2cyc
tdvs
tdvh
tzah
tzad
tenv
tcyc
tack
tds
tdh
tmli
taz
trfs
tsr
trp
tss
tfs
tui
tli
Parameter
Typical sustained average two
cycle time
Cycle
variations ( refer to ATA spec)
Two cycle time allowing for clock
variations ( refer to ATA spec )
Data setup time at recipient
Data hold time at recipient
Data valid setup time at sender
(from data bus being valid until
STROBE edge )
Data valid hold time at sender (from
STROBE edge until data may
become invalid
First STROBE time (for device to
first negate DSTROBE from STOP
during a data-in burst)
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output
drivers to release (from being
asserted or negated)
Minimum delay time required for
output drivers to assert or negate
(from released state)
Envelope time ( from DMACK# to
STOP and HDMARDY# during
data-out burst initiation
STROBE to DMARDY time ( refer
to ATA spec
Ready-to-final-STROBE time ( no
STROBE edges shall be sent this
long
DDMARDY#
Ready-to-pause time ( time that
recipient shall wait to initiate pause
after negating DMARDY# )
Pull-up time before allowing IORDY
to be released
Minimum time a device shall wait
before driving IORDY
Setup and hold times for DMACK#
(before assertion or negation )
Time
negation of DMARQ or assertion of
STOP (when sender terminates a
burst )
after
from
time
STROBE
allowing
the
negation
for
edge
Table 7: OXFW911 Ultra DMA timings
clock
of
to
Mode 0
min
240
112
230
160
15
70
20
20
20
20
50
5
6
0
0
0
0
0
Mode 0
max
230
150
10
70
50
75
20
Mode 1
min
160
156
125
75
10
48
20
20
20
20
50
5
6
0
0
0
0
0
Mode1
max
200
150
10
70
30
70
20
Mode 2
min
120
117
100
55
34
20
20
20
20
50
7
5
6
0
0
0
0
0
Mode 2
max
OXFW911
170
150
10
70
20
60
20
Page 10
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