DS2764 MAXIM [Maxim Integrated Products], DS2764 Datasheet
DS2764
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DS2764 Summary of contents
Page 1
... This low-power device integrates precise temperature, voltage, measurement, nonvolatile (NV) data storage, and Li+ protection into the small footprint of either a TSSOP package or flip-chip package. The DS2764 is a key component in applications capacity estimation, safety monitoring, and battery- specific data storage. PIN CONFIGURATIONS ...
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ABSOLUTE MAXIMUM RATINGS Voltage Range on PLS and CC Pins, Relative to V Voltage Range on Any Other Pin, Relative to V Continuous Internal Sense Resistor Current Pulsed Internal Sense Resistor Current Operating Temperature Range Storage Temperature Range Soldering Temperature ...
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ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUITRY (2.5V £ V £ 5.5V 0°C to +50°C PARAMETER Overvoltage Detect Charge Enable Undervoltage Detect Overcurrent Detect Overcurrent Detect Short-Circuit Detect Short-Circuit Detect Overvoltage Delay Undervoltage Delay Overcurrent Delay Short-Circuit Delay Test ...
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... Note 11: Four-year data retention at +70°C. Note 12: Timing must be fast enough to prevent the DS2764 from entering sleep mode due to bus low for period > Note 13: f must meet the minimum clock low time plus the rise/fall times. SCL ...
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Note 14: The maximum t has only to be met if the device does not stretch the LOW period (t HD:DAT This device internally provides a hold time of at least 300 ns for the SDA signal (referred to the ...
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... Charge Protection Control Output. Controls an external P-channel high-side charge protection FET. Battery Pack Positive Terminal Input. The DS2764 monitors the pack plus terminal through PLS to detect overload and short circuit removal, as well as the presence or removal of a charge source. Additionally, a charge path to recover a deeply depleted cell is provided from PLS to V ...
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... This low-power device integrates precise temperature, voltage, and current measurement, nonvolatile (NV) data storage, and Li+ protection into the small footprint of either a TSSOP package or flip-chip package. The DS2764 is a key component in applications including remaining capacity estimation, safety monitoring, and battery-specific data storage. ...
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... CONFIGURATIONS ONLY. 1kW 1kW DS2764 PLS DD DC SCL V SNS SS 104 V SNS SS V SNS SS PS SDA IS1 IS2 104 R SNS (NOTE 1) SNS R KS IS2 BAT+ 150W 150W CLOCK 150W DATA BAT- R SNS-INT (NOTE IS1 VOLTAGE SENSE DS2764 ...
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... TST Overvoltage. If the cell voltage on V delay the DS2764 shuts off the external charge FET and sets the OV flag in the protection register. When the OVD cell voltage falls below charge enable threshold V protection condition prevents it). Discharging remains enabled during overvoltage, and the DS2764 re-enables the charge FET before V < ...
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... Soft Startup. The discharge protection FET is turned on slowly when the DS2764 enters Active mode from Sleep. The soft startup reduces the inrush current that normally occurs when a battery pack is inserted into an un-powered host system. Soft Startup does not reduce inrush currents if the DS2764 is already in Active mode when the battery pack is connected to the un-powered system. ...
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... CURRENT MEASUREMENT In active mode, the DS2764 continually measures the current flow into and out of the battery by measuring the voltage drop across a current-sense resistor. The DS2764 is available in two configurations: 1) internal 25mW current-sense resistor and 2) external user-selectable sense resistor. In either configuration, the DS2764 considers the voltage difference between pins IS1 and IS2 (V resistor ...
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... MSb TEMPERATURE MEASUREMENT The DS2764 uses an integrated temperature sensor to continually measure battery temperature. Temperature measurements are placed in the temperature register every 220ms in two’s-complement format with a 0.125°C resolution over a ±127°C range. Figure 9 shows the temperature register format. Figure 9. Temperature Register Format MSB— ...
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... Register. The PS bit latches a 0 value when a logic low occurs on the PS pin regardless of the operating mode of the DS2764. If the host intends to monitor future PS pin events, it must write the PS bit to ensure that a subsequent low forced on the PS pin is latched into the PS bit. The PS bit value has no effect on operation of the DS2764 and can be ignored if PS pin monitoring is not required ...
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Table 2. Memory Map ADDRESS (HEX) 00 Protection Register 01 Status Register 02–06 Reserved 07 EEPROM Register 08 Special Feature Register 09–0B Reserved 0C Voltage Register MSB 0D Voltage Register LSB 0E Current Register MSB 0F Current Register LSB 10 ...
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... X X—Reserved Bits. PMOD—Sleep Mode Enable. A value this bit enables the DS2764 to enter sleep mode when the bus is low for greater than 2s and to leave sleep mode when the SCL OR SDA line goes high. A value of 0 disables bus- related transitions into and out of sleep mode. This bit is read-only. The desired default value should be set in bit 5 of address 31h ...
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... The new slave address value is effective following the write to 32h, and must be used to address the DS2764 on subsequent bus transactions. The slave address value is not stored to EEPROM until a Copy EEPROM block 1 command is executed. Prior to executing the Copy command, power cycling the DS2764 restores the original slave address value ...
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... DS2764 slave device and a master device at speeds up to 100kHz. The DS2764’s SDA pin operates bi-directionally, that is, when the DS2764 receives data, SDA operates as an input, and when the DS2764 returns data, SDA operates as an open drain output, with the host system providing a resistive pull-up. ...
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... Slave Address Acknowledge cycle. Control of the SDA signal is retained by the DS2764 throughout the transaction, except for the Acknowledge cycles. The master indicates the end of a read transaction by responding to the last byte it requires with a No Acknowledge. This signals the DS2764 that control of SDA is to remain with the master following the Acknowledge clock. ...
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... Read Data Protocol The Read Data protocol is used to read register and shadow RAM data from the DS2764 starting at memory address specified by MAddr. Data0 represents the data byte in memory location MAddr, Data1 represents the data from MAddr + 1 and DataN represents the last byte read by the master. ...
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... The DS2764 can be special ordered with a unique, factory-programmed ID that is 64 bits in length. The first eight bits are the product family code (B0h for DS2764). The next 48 bits are a unique 40-bit serial number followed by 0x64h. The last eight bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 16). The 64-bit ID can be read as 8 bytes starting at memory address F0h ...