DS1821S+TR DALLAS [Dallas Semiconductor], DS1821S+TR Datasheet - Page 13

• Manufacturer Part Number: DS1821S+TR
• Description: Programmable Digital Thermostat and Thermometer
• Manufacturer: DALLAS [Dallas Semiconductor]

Figure 9 illustrates that the sum of T
Figure 10 shows that system timing margin is maximized by keeping T
and by locating the master sample time during read time slots towards the end of the 15 μs period.
READ/WRITE TIME SLOT TIMING DIAGRAM Figure 8
DETAILED MASTER READ 1 TIMING Figure 9
RECOMMENDED MASTER READ 1 TIMING Figure 10
1-WIRE BUS
GND
1-WIRE BUS
GND
1-WIRE BUS
1-WIRE BUS
V
V
GND
V
GND
V
DD
DD
DD
DD
> 1 μs
OF SLOT
START
small
T
INT
15 μs
15 μs
=
small
T
RC
=
MASTER WRITE “0” SLOT
MASTER READ “0” SLOT
T
INT
60 μs < T
> 1 μs
MIN
LINE TYPE LEGEND (Figure 8, Figure 9 and Figure 10)
Master samples
15 μs
VIH of Master
DS1821 samples
X
“0” < 120
TYP
Bus master pulling low
Resistor pullup
INIT
45 μs
, T
RC
30 μs
, and T
MAX
13 of 18
> 1 μs
15 μs
15 μs
T
RC
SAMPLE
OF SLOT
START
must be less than 15 μs for a read time slot.
15 μs
15 μs
1 μs < T
1 μs < T
DS1821 pulling low
MASTER WRITE “1” SLOT
> 1 μs
MASTER READ “1” SLOT
Master samples
VIH of Master
REC
REC
Master samples
MIN
<
<
INIT
Master samples
∞
15 μs
∞
and T
DS1821 samples
TYP
RC
as short as possible
30 μs
MAX