DS1685-3_12 MAXIM [Maxim Integrated Products], DS1685-3_12 Datasheet - Page 11

• Manufacturer Part Number: DS1685-3_12
• Description: 3V/5V Real-Time Clocks
• Manufacturer: MAXIM [Maxim Integrated Products]

CONTROL REGISTERS
The four control registers A, B, C, and D reside in both bank 0 and bank 1. These registers are accessible at all
times, even during the update cycle.
Register A (0Ah)
UIP – The update-in-progress (UIP) bit is a status flag that can be monitored. When the UIP bit is a 1, the update
transfer occurs soon. When UIP is a 0, the update transfer does not occur for at least 244µs. The time, calendar,
and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP bit is read-only. Writing
the SET bit in Register B to a 1 inhibits any update transfer and clears the UIP status bit.
DV2, DV1, DV0 - These three bits are used to turn the oscillator on or off and to reset the countdown chain. A
pattern of 01X is the only combination of bits that will turn the oscillator on and allow the RTC to keep time. A
pattern of 11X will enable the oscillator but holds the countdown chain in reset. The next update will occur at
500ms after a pattern of 01X is written to DV0, DV1, and DV2. The oscillator enable bit, DV1, will be set to a 1
when V
DV2 = Countdown Chain
DV1 = Oscillator Enable
DV0 = Bank Select
RS3, RS2, RS1, RS0 – These four rate-selection bits select one of the 13 taps on the 15-stage divider or disable
the divider output. The tap selected can be used to generate an output square wave (SQW pin) and/or a periodic
interrupt. The user can do one of the following:
1)
2)
3)
4)
Table 3 lists the periodic interrupt rates and the square-wave frequencies that can be chosen with the RS bits.
Enable the interrupt with the PIE bit;
Enable the SQW output pin with the SQWE or E32K bits;
Enable both at the same time and the same rate; or
Enable neither.
BIT 7
MSB
UIP
1 – resets countdown chain only if DV1=1
0 – countdown chain enabled
1 – oscillator on
0 – oscillator off
1 – extended registers
0 – original bank
CC
is applied.
BIT 6
DV2
BIT 5
DV1
BIT 4
DV0
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BIT 3
RS3
BIT 2
RS2
BIT 1
RS1
BIT 0
RS0
LSB