DS1643-120 DALLAS [Dallas Semiconductor], DS1643-120 Datasheet - Page 4

• Manufacturer Part Number: DS1643-120
• Description: Nonvolatile Timekeeping RAM
• Manufacturer: DALLAS [Dallas Semiconductor]

DS1643 REGISTER MAP – BANK1 Table 2
OSC = STOP BIT
W
NOTE:
All indicated “X” bits are not dedicated to any particular function and can be used as normal RAM bits.
RETRIEVING DATA FROM RAM OR CLOCK
The DS1643 is in the read mode whenever WE (write
enable) is high and CE (chip enable) is low. The device
architecture allows ripple-through access to any of the
address locations in the NV SRAM. Valid data will be
available at the DQ pins within t
input is stable, providing that the CE and OE access
times and states are satisfied. If CE or OE access times
are not met, valid data will be available at the latter of
chip enable access (t
time (t
is controlled by CE and OE. If the outputs are activated
before t
state until t
CE and OE remain valid, output data will remain valid for
output data hold time (t
until the next address access.
DS1643
041697 4/11
ADDRESS
ADDRESS
1FFE
1FFD
1FFC
1FFB
1FFF
1FFA
1FF9
1FF8
OEA
= WRITE BIT
AA
). The state of the data input/output pins (DQ)
, the data lines are driven to an intermediate
AA
. If the address inputs are changed while
OSC
B
W
X
X
X
X
X
–
7
CEA
OH
) but will then go indeterminate
) or at output enable access
FT
B
X
X
X
R
–
–
–
6
AA
after the last address
B
X
X
X
–
–
–
–
–
5
R
X
B
X
X
–
–
–
–
–
–
4
DATA
=
=
READ BIT
UNUSED
B
X
X
–
–
–
–
–
–
3
WRITING DATA TO RAM OR CLOCK
The DS1643 is in the write mode whenever WE and CE
are in their active state. The start of a write is referenced
to the latter occurring transition of WE or CE. The ad-
dresses must be held valid throughout the cycle. CE or
WE must return inactive for a minimum of t
the initiation of another read or write cycle. Data in must
be valid t
t
be high during a write cycle. However, OE can be active
provided that care is taken with the data bus to avoid bus
contention. If OE is low prior to WE transitioning low the
data bus can become active with read data defined by
the address inputs. A low transition on WE will then dis-
able the outputs t
DH
afterward. In a typical application, the OE signal will
B
X
–
–
–
–
–
–
–
2
DS
prior to the end of write and remain valid for
B
X
–
–
–
–
–
–
–
1
WEZ
after WE goes active.
B
FT =
X
–
–
–
–
–
–
–
0
SECONDS
CONTROL
MINUTES
FREQUENCY TEST
MONTH
HOUR
YEAR
DATE
DAY
FUNCTION
FUNCTION
WR
00–99
01–12
01–31
01–07
00–23
00–59
00–59
prior to
A